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As technology scales, the protection of Finite State Machines' (FSMs) states against single event upset (SEU) and multiple bit upsets (MBUs) becomes more difficult. In this paper, a self-checking approach to enhance the SEU/MBUs immunity of FSMs' states by replicating One-Hot code times for state encoding is presented. This approach can correct less than bit-flip faults in the state register per cycle. Bit-flips are treated as random events and modeled by applying Poisson distribution. Two characteristics of this approach are obtained through probability analysis: first, this approach performs better with the increase of , whereas worse when an FSM contains more states; second, this approach can offer more enhanced reliability than Binary or One-Hot state encoding with Triple Modular Redundancy (TMR). The former characteristic leads to the further improvement of this approach which is called state-reforming. The reliabilities of this proposed approach and its state-reformed solutions, as well as are all evaluated through simulations of fault injections.

A transfer transistor structure achieving complete charge transfer in a CMOS image sensor pixel is proposed to eliminate image lag. This structure adopted double N implants for photodiode to ensure a wide channel of charge transfer, a surface P type preventing from dark current and especially a non-uniform doped poly-silicon gate to adjust the potential profile in channel. The simulation results show that if a light pulse of 10000lux illuminates for one integration cycle, the signal voltage of the following frame drops to 1/50000 of the first one. The electron density in N buried layer after charge transfer is around 108/cm3, far below the intrinsic value.

In order to ensure the PSNRs of the demosaiced images of CMOS image sensor and reduce the computational cost at the same time, the proposed demosaicing algorithm in this paper improves on adaptive edge sensitive algorithm and fuzzy assignment algorithm. In order to estimate the direction of edges more accurately, it adds two adjacent pixels of the current pixel as the judgment condition and classifies the edges into strong edges and weak edges. The proposed algorithm adopts fuzzy assignment algorithm to estimate the missing green value at red/blue pixels and assigns different weighting factors according to the results of edge detection. Our comparison on PSNRs and computational cost with several other typical algorithms is performed on Kodak photo CD data sets. The results show that the PSNR value of the G channel improves 1.99dB more than the adaptive fuzzy assignment algorithm and improves about 0.66dB more than the complex algorithm based on variance of color differences and weighing based algorithm. However, the addition operation of the proposed algorithm is only one-fifth of the algorithm based on variance of color differences with nearly the same multiplication and bit-shift operations. The proposed algorithm can get similar PSNRs without affecting the quality of the image and at the same time reduce the computational cost.

This paper presents a novel on-chip image processing architecture with CMOS image sensor, which applies APB bus to implement image processing. The proposed architecture presents the issues related to color image processing and gives the differences between the proposed architecture and the traditional image processing pipeline used in digital still cameras. Considering the hardware implementation and power requirement, this paper combines two efficient auto white balance method together to adjust the three independent color channels. By applied on FPGA, the proposed method can greatly enhance the image quality of raw data. The results show that the proposed image processing architecture and the auto white balance algorithms work well on FPGA development board.

A new algorithm for removing pixel cross-talk effect in CMOS image sensors with Bayer color filter array is proposed. With the assumption that color differences within small neighbors of an image is constant, the algorithm uses the R or B components of raw data to compensate the adjacent G component before color interpolation in order to eliminate the effects that R component interferes with Gr and B component interferes with Gb. The algorithm has low computational complexity. By simulation experimentation on Macbeth color chart and real images, the algorithm is proved to be effective and produces better quality images with conventional color interpolation methods. Finally, the paper design its VLSI frame and validates it with FPGA. The results of test indicate that the algorithm uses fewer hardware resources and can work in real-time completely.

In this paper, a new fast block matching algorithm is developed for motion estimation. The motion estimation algorithm use improved 3-step block matching (ITSS) algorithm that can produces better quality performance and less computational time compared with three-step search (TSS) algorithm and correct the motion vector by using Zero Detection and vector filter. From the experimental results, the proposed algorithm is superior to TSS in both quality performance and computational complexity.

This paper propose a new weighted-adaptive frame rate up-conversion method. The motion estimation algorithm use improved 3-step block matching (ITSS) algorithm, and correct the motion vector by using Zero Detection and vector filter. In addition, weighted-adaptive motion compensation interpolation (WAMCI) increases the adaptability and improves the image quality. The method was validated by FPGA.

Wafer mapping techniques originated at the wafer fab for wafer manufacturing process control and yield improvement as presented by T. Takeda (1994). Recently, inkless assembly processes have been becoming more and more popular for wafer fab process simplification and cycle time reduction, as well as the graded IC product sale under the pressure of IC manufacturing cost. However, not all of the packaging and assembly houses are ready for wafer mapping, as converting from the current inked wafer process to inkless assembly includes a lot of challenges to assembly equipment, process and manufacturing control, especially for smaller die sizes (less than 1times1mm). This paper discusses the critical challenges of handling inkless wafers to packaging and assembly. Technical solutions are developed including error-proof inkless packaging process flow, reference die design, inkless die pick up arithmetic, and pattern recognition optimization. The scenarios of fatal impact to inkless wafer mapping implementation are captured and solutions are provided that guarantee smooth implementation of inkless assembly

With the popularity of the mobile and handset electronic product, there is a stringent requirement on IC package size, weight and thermal/ mechanical integrity. To be smaller, lighter and faster, traditional IC packaging is undergoing an evolution to achieve further miniaturization. Less than 1.0mm CSP BGA with die to package ratio larger than 0.78 was developed to provide such a miniaturization solution to mobile electronic product manufacturer. A series of packaging challenges were encountered when trying to scale down the traditional BGA packages, DAF (die attach film) heating induced strip warpage and post mold cure strip warpage are two key issues which have great impact on package manufacturability. Frequent substrate alignment alarm during die bonding, missing ball during ball attach process and insufficient sucking vacuum during saw singulation are three key showstoppers in qualifying this package for mass production. Thermal mechanical simulation was conducted to analyze the CTE/modulus mismatch induced mold strip warpage, Substrate was re-designed and new compound were evaluated based on the improvement direction given through simulation analysis. Full auto assembly operation was achieved through process/ material improvement for this low profile CSP BGA package.

A novel high temperature pressure sensor is designed by the authors. It is based on a SOI construction, replacing the traditional pn junction insulation with SiO/sub 2/ insulation. The dielectric isolation guarantees low leakage current at high temperature. Thus, the sensors could be used in a high temperature environment. In this paper, a series of SOI high temperature sensors were simulated and analyzed by ANSYS software. The influence of thickness and length-width ratio of the strain diaphragm on the theoretical output was discussed. Accordingly, an optimal design of the strain diaphragm was presented and the location of the piezoresistors was determined. Finally, the sensors were fabricated according to the layout, and then tested. The test results showed that the actual measurement values are consistent with the simulation. The output voltage keeps good linearity with input pressure even at high temperatures. The properties of the product are satisfactory.