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The problem that the conventional double-exponential transient current model (DE model) can overdrive the circuit, which leads to the overestimation of the soft error rate of the logic cell, is solved. Our work uses a new and accurate model for predicting the soft error rate that brings the soft error rate closer to the actual. The piecewise double-exponential transient current model (PDE model) is chosen, and the accuracy of the model is reflected using the Layout Awareness Single Event Multi Transients Soft Error Rate Calculation tool (LA-SEMT-SER tool). The model can characterize transient current pulses piecewise and limit the peak current magnitude to not exceed the conduction current. TCAD models are constructed from 28 nm process library and cell layouts. The transfer characteristic curves of devices are calibrated, and functional timing verification is performed to ensure the accuracy of the TCAD model. The experimental results show that the PDE model is not only more consistent with TCAD simulation than the DE model in modeling the single event transient currents of the device, but also that the SER calculated by the LA-SEMT-SER tool based on the PDE model has a smaller error than the SER calculated by the LA-SEMT-SER tool based on the DE model. [ABSTRACT FROM AUTHOR]

With the rapid development of semiconductor technology, the reduction in device operating voltage and threshold voltage has made integrated circuits more susceptible to the effects of particle radiation. Moreover, as process sizes decrease, the impact of charge sharing effects becomes increasingly severe, with soft errors caused by single event effects becoming one of the main causes of circuit failures. Therefore, the study of sensitivity evaluation methods for integrated circuits is of great significance for promoting the optimization of integrated circuit design, improving single event effect experimental methods, and enhancing the irradiation reliability of integrated circuits. In this paper, we first established a device model for the charge sharing effect and simulated it under reasonable conditions. Based on the simulation results, we then built a neural network model to predict the charge amounts in primary and secondary devices. We also propose a comprehensive automated method for calculating soft errors in unit circuits and validated it through TCAD simulations, achieving an error margin of 2.8–4.3%. This demonstrated the accuracy and effectiveness of the method we propose. [ABSTRACT FROM AUTHOR]

This article presents a radiation-hardened voltage reference and a radiation-hardened low-dropout (LDO) voltage regulator manufactured in bipolar technology for space environment applications. The output of voltage reference is adjustable in 2.5 V ∼ 30 V, with a supply voltage of 24 V. The LDO regulator operates from an input voltage range of 2.5–26 V and provides an output voltage of 1.5 V, with output voltage accuracy of ±0.5 %. The dropout voltage <700 mV at the full load current of 7A. It achieves line regulation and load regulation are <0.5 % over the entire operating temperature range. Through the circuit design of radiation hardening and the optimization of anti-radiation technology, both power management chips have single-event transient (SET) immunity at linear energy transfer (LET) of 37.4 MeV·cm2/mg. The output voltage deviation of rad-hard voltage reference is <0.6 % with total dose radiation tolerance of 100krad(Si) at 0.1 rad(Si)/s. • A radiation-hardened voltage reference for space environment applications. • A radiation-hardened low-dropout (LDO) regulator for space applications. • Circuit design and process optimization hardening (Design-Technology-Co-Hardening). [ABSTRACT FROM AUTHOR]