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The Internet of Things (IoT) is an interface with the physical world that usually operates in random-sparse-event (RSE) scenarios. This article discusses main challenges of IoT chips: power consumption, power supply, artificial intelligence (AI), small-signal acquisition, and evaluation criteria. To overcome these challenges, many works recently aimed at IoT system design have emerged. This work reviews the architecture and circuit innovations that have contributed to IoT developments. This paper does not cover security of IoT. Event-driven architectures and nonuniform sampling ADCs significantly reduce the long-term average power. Besides, embedding AI engines in IoT nodes (AIoT) is one critical trend. The computing-in-memory technique improves the energy efficiency of the AI engine. Asynchronous spike neural networks (ASNNs) AI engines show low power potential. In addition to data processing, small-signal acquisition is also critical. The charge-domain analog-front-end (AFE) techniques such as floating inverter-based amplifiers improve energy efficiency. In addition to the above low power and high energy efficiency technologies, energy harvesting can also enhance the lifetime of AIoT devices. This article discusses recent ambient RF and natural energy harvesting approaches and high-efficiency DC-DC with a wide load range. Finally, novel evaluation criteria are introduced to establish benchmark standards for AIoT chips.

This article presents a 148-nW always-on wake-up system that drastically reduces the system power consumption of Internet of Things (IoT) sensor nodes while oftentimes operating in random-sparse-event (RSE) scenarios. To significantly reduce the long-term average (LTA) power consumption and realize multiapplication and intelligent event detection, three techniques are proposed: 1) In a three-stage pipelined event-driven architecture, a frame generator and a convolutional neural network intelligent inference engine (CNN IIE) in stage III are event-driven by the preliminary detectors in stage II, and the detectors are triggered by a level-crossing (LC) analog-to-digital converter (ADC), i.e., stage I, dramatically reducing the overall power consumption. 2) The clock-free pulse-based instant rate of change (IROC) feature extractor directly processes the asynchronous pulses of the LC-ADC outputs in the temporal domain instead of utilizing a conventional power-hungry frequency-domain method. 3) A reconfigurable IROC, the frame generator, and the CNN IIE provide adaptive intelligence for various IoT events, enhancing the accuracy of multipurpose detection with ultralow power. We demonstrate two artificial intelligence IoT (AIoT) applications at 0.6-V VDD. For electrocardiogram (ECG) recognition, one example works at a typical event rate (ER) of ~4800/h, with an active power of 1.68 $\mu \text{W}$ and a precision of up to 99%; the other is used for keyword spotting (KWS), where the chip achieves 378 nW at ~720/h ER and 94% accuracy. The LTA power is bounded to 148 nW, while the event-driven chip is on call and waiting for events; this chip dominates the AIoT device battery life in RSE scenarios.

This work presents an ultra-low-power software-defined always-on wake-up system to drastically decrease the system power of Internet of Things (IoTs) devices, which usually operate in random-sparse-event (RSE) scenarios. It mainly thanks to a clock-free time-shielding level-crossing ADC (TS-LCADC), software-defined clock-free multi-function detectors, and an asynchronous pipelined event-driven architecture. First, by quantifying RSE noisy signals with clock-free adaptive sampling in a signal-noise-rejecting manner, the proposed TS-LCADC reduces number of sampling points and power, and consumes only 41 nW when on-call waiting for IoT events. Second, the proposed clock-free multi-function detectors with offline and online programmability are able to character the signal features of versatile IoTs events and allow versatile and dynamic wake-up functions. Third, the proposed asynchronous pipelined event-driven architecture minimizes the system activity and thus power, because a power-hungry high-performance system (HPS) is only woken up when a detected parameter crosses its corresponding threshold. As such, the long-term average power (LTA-power) is dominated by the always-on circuits in RSE scenarios. The measurement results achieve 71–75 nW for three typical applications, i.e., heart rate, epilepsy, and keyword envelope detection. The LTA power is only 57 nW when waiting for RSE events, which is 30 $\times $ lower than a prior general-purpose wake-up chip. Compared with other works of dedicated voice and acoustic wake-up functions, this work consumes 2 $\times $ and 17 $\times $ less power, respectively, while featuring 16 $\times $ higher signal bandwidth and a broader versatility.

Power is becoming a major bottleneck in energy constraint applications such as internet-of-things (IoT). Emerging steep-slope devices such as tunnel FETs (TFET) and negative capacitance (NC) FETs are promising candidates for such type of applications. Nevertheless, due to the time-consuming characterization process and inconsistent evaluation criteria, conventional co-design and co-optimization process between novel devices and logic circuits takes too much time and its results rarely meet expectation. As a result, conventional co-design and co-optimization are quite inefficient. In this paper, for the first time, a new criterion is utilized to evaluate novel steep-slope devices for ultra-low power applications. In addition, an efficient evaluation method is proposed, which not only quantitatively guides device design, but also evaluates devices from a circuit perspective without the need for device compact model and circuit simulation. From a device design perspective, optimal design metrics of novel steep slope devices such as average subthreshold slope ( $SS_{avg}$ ), off current ( ${I} _{OFF}$ ), and on current ( ${I} _{ON}$ ) can be directly figured out with the help of the proposed evaluation criteria and method. From a circuit design perspective, the proposed evaluation criteria and method can be used to determine application scope.

Tunnel FET is recognized as one of the most promising candidates for ultra-low power applications due to its ultra-low off current and CMOS compatibility. However, some characteristics of TFET caused by asymmetric device structure and special conduction mechanism may make conventional topologies of logic circuits no longer applicable. Our previous work has reported that TFET stacking will result in severe current degradation, which makes traditional logic cells not applicable. In this paper, two solutions are proposed: first, from a logic cell perspective, novel hybrid TFET-MOSFET topologies of standard logic cells are proposed, which achieve more than 2 times lower hardware cost and intrinsic delay, hence up to 4 times lower area-power-delay product (APDP) than that of conventional TFET logic circuits. Compared to MOSFET logic circuits, the designs achieve almost 2 orders of magnitude lower power and up to 34 times lower APDP. Second, from a large-scale circuit perspective, an optimized digital front-end (DFE) is proposed. Taking serial peripheral interface (SPI) as an example, SPI circuit using the optimized DFE achieves 46% lower delay and 4 times lower APDP than that of traditional TFET SPI, and 3 orders of magnitude lower static power and APDP than that of MOSFET SPI.

In this letter, an occupancy probability prediction (OPP) model is proposed for predicting the trap occupation states of random telegraph noise (RTN) under complex gate bias waveforms. This compact model is developed based on the random charging/discharging behaviors. It is verified by both theoretical simulations and experimental results. The model enables one to evaluate the state of each trap at any time under arbitrary bias, which is helpful for analyzing and simulating the trap-related reliability and variability issues in circuits.

WNT10A (Wingless-type MMTV integration site family, member 10A) plays a crucial role in tooth development, and patients with biallelic WNT10A mutation and mice lacking Wnt10a show taurodontism. However, whether epithelial or mesenchymal WNT10A controls the initiation of the root furcation formation remains unclear, and the functional significance of WNT10A in regulating root morphogenesis has not been clarified. Here, we investigated how Wnt10a affects tooth root development by generating different tissue-specific Wnt10a conditional knockout mice. Wnt10a knockout in the whole tissue ( EIIa-Cre;Wnt10aflox/flox) and in dental epithelium ( K14-Cre;Wnt10aflox/flox) led to an absence of or apically located root furcation in molars of mice, a phenotype that resembled taurodontism. An RNAscope analysis showed that the dynamic epithelial and mesenchymal Wnt10a expression pattern occurred during root development. Immunofluorescent staining of E-cadherin and EdU revealed decreased epithelial cell proliferation at the cervical region of the molar in K14-Cre;Wnt10aflox/floxmice at postnatal day 0 (PN0), just before the initiation of root morphogenesis. Interestingly, we found increased pulpal mesenchymal cell proliferation in the presumptive root furcating region of the molar in K14-Cre;Wnt10aflox/floxmice at PN4 and PN7. RNA-seq indicated that among the Wnt ligands with high endogenous expression levels in molars, Wnt4 was increased after epithelial knockout of Wnt10a. The RNAscope assay confirmed that the expression of Wnt4 and Axin2 in the dental papilla of the presumptive root furcating region, where dental pulp overgrowth occurred, was increased in K14-Cre;Wnt10aflox/floxmolars. Furthermore, after suppression of the elevated Wnt4 level in K14-Cre;Wnt10aflox/floxmolars by Wnt4 shRNA adenovirus and kidney capsule grafts, the root furcation defect was partially rescued. Taken together, our study provides the first in vivo evidence that epithelial Wnt10a guides root furcation formation and plays a crucial role in controlling the organized proliferation of adjacent mesenchymal cells by regulating proper Wnt4 expression during root furcation morphogenesis.

Summary Young donors are reported to be associated with better transplant outcomes than older donors in allogeneic hematopoietic stem cell transplantation (allo-HSCT), but the mechanism is still unclear. The current study compared the different subsets of haematopoietic stem cells (HSCs) and their progenitors as well as immune cells in bone marrow (BM) between young and older donors. The frequencies of HSCs, multipotent progenitors (MPPs) and myeloid progenitors, including common myeloid progenitors (CMPs) and megakaryocyte–erythroid progenitors (MEPs), were decreased, whereas those of lymphoid progenitors, including multi-potent lymphoid progenitors (MLPs) and common lymphoid progenitors (CLPs), were increased in the BM of young donors compared with in that of older donors. Lower reactive oxygen species (ROS) levels were observed in BM HSCs and six progenitor lines in young donors. Furthermore, young donors demonstrated higher frequencies of naive T cells and immune suppressor cells, such as alternative macrophages (M2) and lower frequencies of memory T cells and immune effectors, including T helper-1 and T cytotoxic-1 cells, in BM than older donors. Multivariate analysis demonstrated that donor age was independently correlated with BM HSC frequency. Although further validation is required, our results suggest that the differences in the frequency and immune differentiation potential of HSCs in BM between young donors and older donors may partly explain the different outcomes of allo-HSCT.

IoT devices usually operate in random-sparse-event scenarios (Fig. 20.2.1). To avoid missing events, traditionally a periodic-wake-up frequency [1] must be orders of magnitude higher than the average event rate, wasting huge power. An emerging event-driven approach seeks to trigger a power-hungry highperformance system (HPS) using an ultra-low-power wake-up circuit. State-of-the-art wake-up chips with DSP-based and neural-network-based feature extraction consume 12nW [2], 1µW [3], and 142nW [4]. However, they can only respond to dedicated voice/acoustic signal of low bandwidth. Another wake-up chip with 2.2µW power [5] shows potential for general purpose use, however, the pattern recognition technology is complicated and power hungry for many IoT devices. Considering the cost, the versatile and continuously emerging IoT applications, and time-to-market, a general-purpose wake-up chip defined by software with ultra-low power is highly desired, but not yet reported.

A parameter extraction methodology of statistical process variations in FinFET is presented in this paper. First, the main impacts of various variation sources are decomposed, with detailed discussion on the correlation between threshold voltage and subthreshold swing. Second, following the Fin-edge roughness (FER) and gate-edge roughness (GER) compact models, the physical parameters, autocorrelation length and amplitude of root mean square of FER and GER, are extracted based on our proposed extraction procedure. Given a set of ${I}$ – ${V}$ (whether from TCAD or measured silicon data), this method can simply extract the process variation parameters from several experimental sets, such as experiments under different device geometries and/or bias conditions. With the extracted parameters integrated into compact models, the figure of merits of simulation program with integrated circuit emphasis results are well consistent with experimental measurements. The proposed methodology is not only helpful for model-based design-technology co-optimization, but also helpful for variation-aware circuit design.

With the downscaling of CMOS devices, dynamic variability induced by negative bias temperature instability (NBTI) has become a critical issue. In addition to the time-dependent device-to-device variation (DDV) of NBTI degradation, the cycle-to-cycle variation (CCV) originated from random trap occupation is found non-negligible and should be added into the total dynamic variation. This paper summarizes our recent studies on NBTI-induced dynamic variability, focusing on the CCV effect, with more details on the statistical modeling, circuit reliability simulation methodologies and experimental results. By adding the random trap occupation into consideration, a statistical model for total dynamic variation (DDV + CCV) is proposed. The effective occupancy probability peff is introduced as a key parameter for modeling and circuit reliability simulation. With the statistical trap response (STR) method and modified on-the-fly method, the proposed model is validated by the experimental evidence under both DC and AC NBTI. According to the model and experimental results, circuit reliability simulation framework is proposed for both long-term quasi-static and short-term transient performance evaluation with the additional impact of CCV. Two representative digital circuit units, ring oscillator (RO) and SRAM cell, are simulated under different conditions, indicating it necessary to consider the evident influence of the CCV in accurate circuit reliability evaluation. The results are helpful for the reliability/variability-aware circuit design in nanoscale technology.

Vgmax Hot-Carrier-Injection (HCI) degradation in Multi-finger p-Laterally-Diffused Metal-Oxide-Semiconductor Field-Effect-Transistors (LDMOSFET) had been investigated by Multi-Region Direct-Current-Current-Voltage (MR-DCIV) characterization method-probing the interface state distribution along the channel, accumulation and (Shallow Trench Isolation) STI-drift region. The method feasibility was verified by device simulation and stress experiment. The enhanced interface state generation in the channel and accumulation region was clearly revealed in multi-finger layout device. This layout dependent degradation was associated with self-heating effect and temperature accelerated Vgmax HCI stress.

We investigate the impact of the encapsulation with hexagonal boron nitride (h-BN) on the Raman spectrum of few layer black phosphorus. The encapsulation results in a significant reduction of the line width of the Raman modes of black phosphorus, due to a reduced phonon scattering rate. We observe a so far elusive peak in the Raman spectra $\sim$4cm$^{-1}$ above the A$_{\text{g}}^1$ mode in trilayer and thicker flakes, which had not been observed experimentally. The newly observed mode originates from the strong black phosphorus inter-layer interaction, which induces a hardening of the surface atoms vibration with respect to the corresponding modes of the inner layers. The observation of this mode suggests a significant impact of h-BN encapsulation on the properties of black phosphorus and can serve as an indicator of the quality of its surface., Comment: 15 pages, 4 figures just accepted for publication in Nanoscale http://pubs.rsc.org/en/Content/ArticleLanding/2017/NR/C7NR05588A#!divAbstract

In this paper, a novel heterostacked tunnel FET (HS-TFET) is proposed for steeper average subthreshold swing (SS). Different from conventional TFETs, HS-TFETs owns a stacked source configuration consisting of an upper source layer with a relatively larger bandgap material and an underlying source layer with smaller bandgap materials. Since smaller bandgap materials exhibit much higher band-to-band tunneling efficiency, the underlying layer of HS-TFET could provide extra drain current increment with increasing gate voltage, and thus effectively improve the subthreshold characteristics for steeper average SS. The simulation results show that the proposed Si–Ge-based HS-TFET can achieve much steeper average SS (25 mV/decade) than conventional Si TFET (42 mV/decade), exhibiting more than one decade higher I60 without leakage current degradation.

Tunnel FET (TFET) is recognized to be one of the most promising candidates for ultra-low power applications due to its ultra-low off current and high compatibility with CMOS process. However, different from the typical features of MOSFET, some electrical characteristics of TFETs caused by asymmetric device structure and special conduction mechanism may make conventional topologies of circuits no longer applicable. In this paper, it is found that the TFETs stacking will result in severe current degradation behavior, which makes traditional topologies of logic gates may be not applicable. To solve this problem, a set of novel hybrid TFET-MOSFET topologies for standard logic cells are proposed. The proposed designs achieve more than 2 times lower hardware cost and intrinsic delay, and realize up to 4 times lower area-power-delay product (APDP) than that of conventional TFET-based logic circuits. Moreover, the proposed topologies can achieve almost 2 orders of magnitude lower power and up to 34 times lower APDP than that of conventional MOSFET-based logic circuits. The proposed standard logic cells show great superiority for power-constraint applications.

In this paper, we propose a machine-learning assisted modeling framework in design-technology co-optimization (DTCO) flow. Neural network (NN) based surrogate model is used as an alternative of compact model of new devices without prior knowledge of device physics to predict device and circuit electrical characteristics. This modeling framework is demonstrated and verified in FinFET with high predicted accuracy in device and circuit level. Details about the data handling and prediction results are discussed. Moreover, same framework is applied to new mechanism device tunnel FET (TFET) to predict device and circuit characteristics. This work provides new modeling method for DTCO flow.