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With the use of CCl4, which has been utilized as a p-type dopant source for carbon doping of GaAs epilayers during MOVPE growth, very novel growth behaviors of GaAs and AlGaAs layers are observed. It is shown that the CCl4 flow rate is a very important parameter which controls the lateral growth rate on patterned substrates. The ratio of lateral to vertical growth rate of GaAs is increased up to 14 with the CCl4 flow rate. The lateral growth rates of GaAs and AlGaAs can be described as linear functions of CCl4 flow rate. The increase of GaAs lateral growth rate is more remarkable than AlGaAs. This novel characteristic is utilized in fabricating very novel quantum wire structures on V-grooved substrate. Unlike the undoped quantum wire, CCl4-doped quantum wire shows a very large thickness enhancement factor and a unique feature in its shape.

We have investigated the facet evolution of Al 0.5 Ga 0.5 As GaAs multilayers on mesa- or groove-patterned GaAs substrates during metalorganic chemical vapor deposition (MOCVD) as a function of growth temperature and CCl4 flow rate. Instead of the conventional evolution of a (433)A side wall facet for undoped Al 0.5 Ga 0.5 As GaAs multilayers on a mesa, we have observed (511)A or (411)A facet evolutions during MOCVD growth in the presence of CCl4. In addition, the ratio of the growth rates of both GaAs and Al0.5Ga0.5As on the side wall facets and the (100) mesa top are remarkably enhanced compared to the growth without CCl4. Additionally fast planarization on a groove, which is desirable for device application, has been observed. The growth rate ratio shows strong dependencies on growth temperature and CCl4 flow rate indicating that the CCl4 supply rate can be an adequate parameter for lateral growth control. Using these characteristics, we have fabricated CCl4-doped quantum wires (QWRs) on V-groove structures. Extremely enhanced thickness of the QWR on a V-groove due to CCl4 effect is observed.

We integrate FinFET DRAM in sub-60nm feature size. To avoid severe passing gate effects in FinFET cell array, we introduce a local damascene gate structure. Threshold voltage control of the ultra thin body transistors is successfully achieved by adopting p+ boron in-situ doped poly-silicon gate on the FinFET cells. As a result, very stable and uniform operation of FinFET cells is realized. The local damascene FinFET with p+ gate can become a highly feasible mainstream DRAM technology for sub-60nm low-power high-speed devices

90 nm DRAM technology and beyond requires the robust memory cell capacitor structure in order to increase cell capacitance for high performance and low power applications. Thus, the cell technology must have the feature of high capacitance of memory cell capacitor while maintaining its mechanical stability. To accomplish these purposes, we develop the multi-stack storage node structure whose enlarged bottom size of OCS(One Cylindrical Storage node) can give much better mechanical stability of the capacitor than that of the conventional capacitor. Using Al/sub 2/O/sub 3//HfO/sub 2/ dielectric material together with this structure can give high cell capacitance 30fF/cell and low leakage current less than 1fA/cell.

We have observed the remarkable increase of GaAs lateral growth rate in the presence of CCl4 during metalorganic chemical vapor deposition (MOCVD) on patterned GaAs substrates. The lateral growth rate shows a linear dependence on CCl4 flow rate. On the other hand, the GaAs vertical growth rate is relatively insensitive to the CCl4 flow rate. The maximum ratio of lateral to vertical growth rate is about 14. Using these characteristics, we have fabricated CCl4‐doped quantum wires (QWRs) on V‐groove structures. The QWR structures show thickness enhancement factors, defined as the ratio of QWR thickness in the center region to the quantum well thickness in the nonpatterned region, as high as 5.6.

For the first time, 512 Mb DRAMs using a Recess-Channel-Array-Transistor(RCAT) are successfully developed with 88 nm feature size, which is the smallest feature size ever reported in DRAM technology with non-planar array transistor. The RCAT with gate length of 75 nm and recessed channel depth of 150 nm exhibits drastically improved electrical characteristics such as DIBL, BV/sub DS/, junction leakage and cell contact resistance, comparing to a conventional planar array transistor of the same gate length. The most powerful effect using the RCAT in DRAMs is a great improvement of data retention time. In addition, this technology will easily extend to sub-70 nm node by simply increasing recessed channel depth and keeping the same doping concentration of the substrate.