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A switchable bandstop filter is proposed herein. In order to achieve switchability between a single ultra‐wide stopband and dual wide stopbands, a complex process of coupling synthesis is not necessarily required. By setting two diodes at the input and output port separately, this bandstop filter can be switched between single and dual stopbands. An exemplary bandstop filter with central frequency at 2 GHz is fabricated on Rogers RO4003C, a substrate with a thickness of 0.813 mm and an area occupying 29.3 × 29.7 mm. Agreement between the theoretical and measured results can validate the proposed circuit.

This study presents a new virtual inductor current circuit to reduce circuit complexity, which is not necessary to sense inductance current directly. The buck converter was designed to produce an output voltage of 1.0–2.5 V for a 3.0–3.6 V input voltage. The load current range was from 100 mA to 500 mA. It was simulated and verified by SIMPLIS and MathCAD. The simulation results of this buck converter show that the voltage error is within 1%, and the recovery time is smaller than 2 ms for step-up and step-down load transients. Additionally, it achieves less than 26 mV overshoot at full-load step transient response. The circuit topology would be able to fabricate using TSMC 0.35 mm 2P4M CMOS technology. The control mechanism, implementation, and design procedure are presented in this paper.

In this study, a switchable bandstop filter is proposed. In order to achieve the switchability between a single ultra-wide stopband and dual wide stopbands, the complex process of coupling synthesis is not required. By setting two diodes at the input and output port separately, this bandstop filter can be switched between single and dual stopbands. An exemplary bandstop filter with the central frequency at 2 GHz is fabricated on Rogers RO4003C, the substrate with thickness of 0.813 mm and with an area occupying 29.3 mm × 29.7 mm. The agreement between theoretical and measured results can validate our proposed circuit.

The object tracking devices are implemented as embedded systems that are deployed at crossroads and streets for crime, environment and traffic surveillance. As hundreds of thousands of object tracking devices persistently and simultaneously work every second resulting huge energy consumption. This work proposes befitting continuous-time model for object tracking networks to achieve energy saving. First, each object tracking device is represented as a set of sequence class. Second, the number of cooperating object tracking device is clustered for alternate work. Next, we derive a formula to fast assessing energy consumption for object tracking devices at crossroads or streets. Finally, we simulate the energy consumption of object tracking devices at crossroads or streets and the simulation results gain the effectiveness for energy saving.

Embedded systems are generally designed for specific purpose such as alarm systems and learning systems. These devices work in particular scenario and repeatedly perform a few particular tasks, which result in the shortage of extensible ability to execute diverse tasks. This work proposes software synthesis algorithms for generating code which can execute on embedded ubiquitous learning system. Moreover, the extensible problem is solved by extensible software synthesis (E2S) technique. The E2S comprises CEO, CEOAS, CBOAS and CTOAS procedures that are developed for synthesizing software with extensible ability. Each procedure first separately synthesizes its extensible component, so-called EC, and then applies it to construct the various tasks. Next, the E2S synthesizes various ECs to generate codes to serve complex and diverse functionalities. The synthesis codes are verified on an ARM emulation platform. Experimental results on benchmarks show the E2S achieves not only extensible ability but also the time of software synthesis which meets the requirement of specification.

Grey relational clustering is used to minimise wire length during field programmable gate arrays (FPGA) placement and routing. The proposed Grey Relational Clustering Apply to Placement (GRAP) algorithm combines grey relational clustering and convex assigned placement for regular ICs method to construct a placement netlist, which was successfully used to solve the problem of minimising wire length in an FPGA placement. Upon calculating the grey relational grade, GRAP can rank the sequence and analyse the minimal distance in configuration logic blocks based on the grey relational sequence and combined connection-based approaches. The experimental results demonstrate that the GRAP effectively compares the Hibert, Z and Snake with bounding box (BB) cost function in the space-filling curve. The GRAP improved BB cost by 0.753%, 0.324% and 0.096% for the Hilbert, Z and Snake, respectively. This study also compares the critical path with the space-filling curve. The GRAP approach improved the critical path for S...

In recent years, the FPGA performance requirements are changes in the evolution. From the past a static schedule way, development tasks are running to the dynamic scheduling system. This study proposed FPGA dynamic reconfigurable scheduling and placement base on TGFF generated Random standard schedule and Grey relation of grey system. The scheduling method accords to the placement of strategy objectives mentioned in the different tasks and time, while the placement of the ideal state, the FPGA resources will improve utilization, and reduce waste. Finally, the results of the mentioned method strategy the placement make scheduling strategy referred to reach the ideal state.

Hardware-software partitioning in an embedded multiprocessor field programmable gate array (FPGA) system is difficult as such systems are uncertain and constraints are various. Moreover, the effect of relational degree for each partitioning combination of system constraints is too difficult analysis to determine a partitioning result. This work applies grey relational analysis to identify a partitioning result for an uncertain system with multiple constraints. Moreover, the relational effect of each partitioning combination is applied to determine the role of each task as hardware or software. Experimental results indicate that the proposed attains a partitioning result with low power consumption and fast execution time for a benchmark with 199 tasks.

Embedded systems tightly serve the needs of consumer electronics, home automation and portable devices. During the period of developing embedded systems, code generation is always seen a design challenge because every embedded processor has its own specific characteristic. In this paper, we propose a retargetable code generation (RCG) methodology which can generate retargetable C program for embedded processors. In addition, the generated code is further verified for time constraint with the global time, local time and kernel time. Finally, two design examples namely normal traffic light controller (NTLC) and four phases stepping motor control (FPSMC) are used to illustrate the feasibility in the embedded platform.

Embedded system works everywhere for repeatedly performing a few particular functionalities. Well-known products include consumer electronics, smart home applications, and telematics device, and so forth. Recently, developing methodology of embedded systems is applied to conduct the design of cloud embedded system resulting in the applications of embedded system being more diverse. However, the more energy consumes result from the more embedded system works. This study presents hyperrectangle technology (HT) to embedded system for obtaining energy saving. The HT adopts drift effect to construct embedded systems with more hardware circuits than software components or vice versa. It can fast construct embedded system with a set of hardware circuits and software components. Moreover, it has a great benefit to fast explore energy consumption for various embedded systems. The effects are presented by assessing a JPEG benchmarks. Experimental results demonstrate that the HT, respectively, achieves the energy saving by 29.84%, 2.07%, and 68.80% on average to GA, GHO, and Lin.

This paper aims at developing grey relational clustering for FPGA placement. The proposed GRAP (Grey Relational Clustering Apply to Placement) algorithm was combined with grey relational clustering and CAPRI algorithm to successfully solve FPGA placement design problem. Experimental results demonstrate that the GRAP compares the Hilbert, Z and Snake with BB cost function in space filling curve. The GRAP improved BB cost by 0.753%, 0.324% and 0.096% for the Hilbert, Z and Snake, respectively.

Heterogeneous embedded systems are much more diverse in hardware architectures than ever before for processors and peripherals. On the other hand, software deployments are also varied such as service-oriented architecture (SOA), open systems interconnection (OSI) and component-based software development (CBSD). The diverse architectures of hardware and software cause problems corresponding to time-to-market, cost decrease, transparency, scalab ility, flexib ility and maintainab ility. This study proposes software synthesis of middleware which can automatically generate software for heterogeneous embedded system. Moreover, it can be used to solve problems for transparency, scalability, flexibility and maintainability. The effectiveness and feasibility of the proposed approach is demonstrated by two heterogeneous embedded systems. We design e-book system and digital photo frame system to coordinate with software synthesis of middleware on two embedded system platforms. Finally, we evaluate the correction of functionality for two heterogeneous embedded systems.

This work aims at developing grey relational grade for minimal wire length FPGA placement to follow-up the FPGA routing work. The proposed GRAP (Grey Relational Grade Apply to Placement) algorithm was combined with grey relational clustering and CAPRI algorithm to construct a placement netlist to successfully solve minimal wire length in FPGA placement design problem. After the grey relational grade is calculated, GRAP can rank the sequence and analyze the minimal distance in CLB blocks from the grey relational sequence and combine connection-based approaches. Experimental results demonstrate that the proposed algorithm can obtain minimal total wire length.

This work studies how the architectural parameters of LUT-based field programmable gate arrays (FPGAs) are related to the LUT cluster size N and input number k A novel algorithm is proposed to combine grey decision-making approach for solving the problem of FPGA performance. Experimental results demonstrate that the algorithm improves the DAO map+T-VPack delay by 7.27% and reduces the SMAC total of CLB number by 22.15% on average. Furthermore, our proposed can get optimizes performance by appropriate selection of pairs of LUT cluster size N and input number k to construct the FPGA architecture with inequality demandable weight in area, energy, and delay.

An embedded multiprocessor FPGA system can provide powerful and more functionalities than single processor system. However, the hardware-software partitioning problem is more complex in system design because the system components become escalation. In this paper, we propose a sophisticated computation method (SCM) to solve hardware-software partitioning issues for embedded multiprocessor FPGA systems. The SCM consists of two levels partition which includes processors-fit level and multi-fit level constraints. In processors-fit level, the partitioning results of unsatisfying processor constraint can be rapidly eliminated. Next, multi-fit level constraints compute various system constraints that based on divide-and-conquer and exhaust methods. Experimental results show that our proposed method can rapidly obtain better partitioning results.

Hundreds of thousands circuits can not be verified easily while develop a field programmable gate array (FPGA) system. In this paper, we develop a functional verification tool, namely FVT, to verify the designer defined specification of functionalities with simulator and emulator in a FPGA system. In addition, FVT can point out the exact bugs for functionality where locates at specific cycle. Experiment results show that FVT can save time up to 99%.

In this paper, we present hardware-oriented partitioning approach that can solve the partitioning issues for embedded multiprocessor FPGA systems. In addition, it can gain a better partitioning result, faster execution time, less memory and higher slice used rate, under satisfied system constraints. We also demonstrate the feasibility of our approach by a JPEG encoding system using Xilinx ML310 FPGA platform. Experiment results show that the execution time and memory size are improved.