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The devastating Chichi earthquake in Taiwan in 1999 highlighted the importance of disaster prevention and relief operations. In response to the challenge of extreme events and compound disasters, the National Science and Technology Center for Disaster Reduction (NCDR) contributes to operations at the Central Emergency Operation Center (CEOC) of Taiwan by providing integrated information and timely suggestions, and it delivers a common operational picture to central and local governments through a decision support system. This study was undertaken to explore the emergency response towards the reconnaissance of earthquake disasters in Taiwan to illustrate how resilient cities ensure rapid crisis response with a focus on the NCDR disaster response decision support system. This study examines the decision support system used following the 2016 ML 6.6 Meinong earthquake. The results demonstrate that the first line of relief for the emergency response commander is data-driven decision-making. [ABSTRACT FROM AUTHOR]

A triangular-modulated spread-spectrum clock generator using a[DELTA]--[SIGMA]-modulated fractional-N phase-locked loop (PLL) is presented. The PLL employs a multiphase divider to implement the modulated fractional counter with increased [DELTA]--[SIGMA] operation speed. In addition, the phase mismatching error in the phase-interpolated PLL with multiphase clocks can be randomized, and finer frequency resolution is achievable. With a frequency modulation of 33 kHz, the measured peak power reduction is more than 11.4 dB under a deviation of [+ or -] 0.37%. Without spread-spectrum clocking, the PLL generates 2.4-GHz output with 18.82-ps peak-to-peak jitter. After spread-spectrum operation, the measured up-spread and down-spread jitter can achieve 52.59 and 56.79 ps, respectively. The chip occupies 950 x 850 [micro][m.sup.2] in 0.18-[micro]m CMOS process and consumes 36 mW. Index Terms--Fractional divider, fractional-N phase-locked loop (PLL), multiphase signals, phase interpolation, spread-spectrum clock generation (SSCG), [DELTA]--[SIGMA] modulator.

To avoid the acoustic resonance on operating metal halide lamps, an autofrequency-searching method is implemented on the high-frequency electronic ballast. The proposed method allows the use of a high-frequency electronic ballast, making the ballast able to adjust the operating frequency automatically as soon as the acoustic resonance is detected and, consequently, to locate it at a stable frequency. The electronic ballast achieves a high efficiency and a high power density through the employment of a high-frequency resonant inverter with an embedded buck-boost converter for power-factor correction and lamp power regulation. The control strategy is realized by a microprocessor along with the acoustic-resonance detection circuit. The operation of autofrequency searching is illustrated by the experiments on an electronic ballast designed for 70-W metal halide lamps. Index Terms--Acoustic resonance, autofrequency searching, electronic ballast, metal halide lamp.

A low-voltage frequency synthesizer fabricated with a 0.35-[micro]m standard CMOS technology is presented. A1-V dual-modulus prescaler using the dynamic back-gate forward bias method has been developed for low-voltage operation. The prescaler, including a preamplifier, measured at 1-V supply voltage has a maximum operating frequency of 170 MHz, and its power dissipation is only 0.9 mW. The voltage-controlled oscillator (VCO) in the frequency synthesizer is an LC-tank based oscillator. When locked at the oscillation frequency of 148 MHz, the measured phase noise of the VCO is -- 106 dBc/Hz at 100-kHz from the carrier. The whole power consumption of the frequency synthesizer is 10.5 mW.