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5 results on '"Yan-Shiun Wu"'

4. DATC RDF: Robust design flow database: Invited paper

Author

Yan-Shiun Wu, Jinwook Jung, Pei-Yu Lee, Yih-Lang Li, Iris Hui-Ru Jiang, Victor N. Kravets, Gi-Joon Nam, Nima Karimpour Darav, and Laleh Behjat

Subjects
Robust design, Logic synthesis, Database, Flow (mathematics), Computer science, Design flow, Electronic design automation, computer.file_format, Physical design, RDF, computer.software_genre, computer
Abstract

In this paper, we present DATC Robust Design Flow Database covering the stages from logic synthesis to physical design [1]. Based on this database, design flow and cross-stage optimization research can be conducted via various EDA tools developed from academia.

Published
2017

5. Pin accessibility evaluating model for improving routability of VLSI designs

Author

Yan-Shiun Wu, Shinichi Nishizawa, Jun Shiomi, Yih-Lang Li, Hidetoshi Onodera, and Hong-Yan Su

Subjects
Very-large-scale integration, Computer science, Reduction rate, Boundary (topology), Hardware_PERFORMANCEANDRELIABILITY, 02 engineering and technology, Chip, 01 natural sciences, 020202 computer hardware & architecture, 010309 optics, Condensed Matter::Superconductivity, 0103 physical sciences, Hardware_INTEGRATEDCIRCUITS, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Routing (electronic design automation), Block (data storage)
Abstract

Pin accessibility influences the routability of a design at the stage of block/chip assembling. The estimation model for pin accessibility in previous researches counts the total number of intersections between each pin and M2 routing tracks. It does not consider the variation of pin accessibility as the spacing between a pin and its neighboring pins and metal wires changes. Besides, it cannot properly deal with the off-grid pin access neither. In this paper, we propose a general model for pin accessibility estimation. In the model, all directions to connect to the boundary of a pin are under estimation. Off-grid pin access is also available. Experimental results show that the reduction rate of minimum area to complete the routing of a circuit can be 7.0% on average. Due to the diminishment of required area for routing, the total number of vias for higher metal layer also decrease under the same area constraint.

Published
2017

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