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Multinode upset induced by radiation on integrated circuits has caused many circuit reliability issues. This article proposes a single-event quadruple-node upset (QNU) recovery latch (NEST), based on four circular feedback loops that are formed by 25 C-elements to realize high robustness. NEST achieves 29.02% reduction in power consumption compared to the latch design and algorithm-based verification protected against multiple-node upset (LDAVPM) latch and 51.44% reduction in setup time compared to the quadruple-node upset recoverable and high-impedance-state insensitive latch (QRHIL) latch. NEST also achieves a 99.29% QNU recovery rate. Furthermore, a high-speed, high-precision optimization algorithm for multinode upset recovery is also proposed and implemented. This algorithm achieves 99.84 reduction in simulation time for exhaustive fault injections having equivalent accuracy with high performance simulation program with integrated circuit emphasis (HSPICE).

As semiconductor technologies scale down, radiative-particle-induced soft errors and static power consumption are becoming major concerns for digital circuits. Magnetic-tunnel-junctions (MTJs) are widely used to address these concerns. MTJs are nonvolatile (NV) and compatible with traditional CMOS processes. In this article, we first propose a double-node-upset (DNU) tolerant and NV latch, i.e., M-TPDICE-V2, providing high reliability. In addition, we further propose an advanced latch, namely, M-8C, that is able to completely recover from single-node upsets (SNUs) and DNUs. M-8C uses a DNU recovery module and a backup and restore module based on a pair of MTJs. Furthermore, we propose a universal backup and restore module suitable for any latch providing nonvolatility. We simulate the proposed latches using the Synopsys HSPICE tool with a 45-nm CMOS process model. Simulation results confirm the superior capabilities of our proposed M-TPDICE-V2 and M-8C latches. M-TPDICE-V2 exhibits strong SNU and DNU tolerance and nonvolatility, while the M-8C latch provides complete DNU recovery capabilities.

In deep nanoscale and highly integrated complementary metal-oxide-semiconductor (CMOS) technologies, storage circuits are increasingly sensitive to multiple-node upsets (MNUs) caused by charge sharing. In order to mitigate the impact of MNUs, many MNU-hardened latches based on C-elements matrices have been proposed by research scholars. In this article, we analyze and summarize the MNU-hardened latches based on the C-elements matrix, and propose the connection rules and general fault-tolerance principle of the looped C-element matrix. Based on this design idea, we propose a low-overhead and highly reliable quadruple-node upsets (QNUs) self-recovery latch (referred to as QR-R11C2). The proposed latch is based on a looped C-element matrix with 11 rows and 2 columns, forming a heterogeneous interconnect scheme, which can provide complete self-recovery from QNUs in harsh radiation environments. Simulation results show that the proposed latch has the lowest power consumption, area-power-delay product, and setup time among existing QNU self-recovery latches. In addition, this article also analyzes and summarizes the MNU statistics of the looped C-element matrix-based latch designs and proposes an MNU self-recoverability verification method for looped C-element matrix-based latch designs. Taking the example of verifying the self-recoverability of six looped C-element matrix-based latches, the proposed verification method can reduce MNU combinations by 95.24%–99.99% compared to the exhaustive combinations.

The entropy source structure with embedded XOR gates in a ring oscillator (RO) as a true random number generator (TRNG) can improve the speed of accumulating jitter in the oscillator. However, the XOR gate has a certain response time to the input change, and when the input changes too fast, the XOR gate will output short pulses. In this paper, we propose a TRNG design based on a multi-ring convergence oscillator (MRCO) making use of the characteristics of short pulses. We study the output of the XOR gate when facing different inputs. By modeling the time of a fibonacci ring oscillator (FIRO) as an example, we find that the loss of short pulses in an inverter chain is the reason for making the FIRO enter into periodic oscillation. This phenomenon suppresses the accumulation of jitter and occurs periodically in existing structures. Our proposed structure uses independent sub-rings to accumulate jitter, allowing the main-ring to quickly generate short pulses to provide analog randomness. The proposed TRNG design is implemented in Xilinx Virtex-6 FPGA. The experimental results show that it has the highest ratio of throughput rate to hardware resources. The generated random sequence pass both NIST SP800-22 test and NIST SP800-90B test.