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This paper experimentally demonstrates a near-crossbar memory logic technique called Pinatubo. Pinatubo, an acronym for Processing In Non-volatile memory ArchiTecture for bUlk Bitwise Operations, facilitates the concurrent activation of two or more rows, enabling bitwise operations such as OR, AND, XOR, and NOT on the activated rows. We implement Pinatubo using phase change memory (PCM) and compare our experimental results with the simulated data from the original Pinatubo study. Our findings highlight a significant four-orders of magnitude difference between resistance states, suggesting the robustness of the Pinatubo architecture with PCM technology.

Stateful logic is a digital processing-in-memory technique that could address von Neumann memory bottleneck challenges while maintaining backward compatibility with standard von Neumann architectures. In stateful logic, memory cells are used to perform the logic operations without reading or moving any data outside the memory array. Stateful logic has been previously demonstrated using several resistive memory types, mostly by resistive RAM (RRAM). Here we present a new method to design stateful logic using a different resistive memory - phase change memory (PCM). We propose and experimentally demonstrate four logic gate types (NOR, IMPLY, OR, NIMP) using commonly used PCM materials. Our stateful logic circuits are different than previously proposed circuits due to the different switching mechanism and functionality of PCM compared to RRAM. Since the proposed stateful logic form a functionally complete set, these gates enable sequential execution of any logic function within the memory, paving the way to PCM-based digital processing-in-memory systems.

Resistive switching devices herald a transformative technology for memory and computation, offering considerable advantages in performance and energy efficiency. Here we employ a simple and scalable material system of conductive oxide interfaces and leverage their unique properties for a new type of resistive switching device. For the first time, we demonstrate an $\rm Al_2O_3-TiO_2$ based valence-change resistive switching device, where the conductive oxide interface serves both as the back electrode and as a reservoir of defects for switching. The amorphous-polycrystalline $\rm Al_2O_3-TiO_2$ conductive interface is obtained following the technological path of simplifying the fabrication of the two-dimensional electron gases (2DEGs), making them more scalable for practical mass integration. We combine physical analysis of the device chemistry and microstructure with comprehensive electrical analysis of its switching behavior and performance. We pinpoint the origin of the resistive switching to the conductive oxide interface, which serves as the bottom electrode and as a reservoir of oxygen vacancies. The latter plays a key role in valence-change resistive switching devices. The new device, based on scalable and complementary metal-oxide-semiconductor (CMOS) technology-compatible fabrication processes, opens new design spaces towards increased tunability and simplification of the device selection challenge., Comment: Supplementary Material included at the end

Achieving good electrical contacts is one of the major challenges in realizing devices based on atomically thin two-dimensional (2D) semiconductors. Several studies have examined this hurdle, but a universal understanding of the contact resistance and an underlying approach to its reduction are currently lacking. In this work we expose the shortcomings of the classical contact resistance model in describing contacts to 2D materials, and offer a correction based on the addition of a lateral pseudo-junction resistance component (Rjun). We use a combination of unique contact resistance measurements to experimentally characterize Rjun for Ni contacts to monolayer MoS2. We find that Rjun is the dominating component of the contact resistance in undoped 2D devices and show that it is responsible for most of the back-gate bias and temperature dependence. Our corrected model and experimental results help understand the underlying physics of state-of-the-art contact engineering approaches in the context of minimizing Rjun.

Phase change memory (PCM) is one of the leading candidates for neuromorphic hardware and has recently matured as a storage class memory. Yet, energy and power consumption remain key challenges for this technology because part of the PCM device must be self-heated to its melting temperature during reset. Here, we show that this reset energy can be reduced by nearly two orders of magnitude by minimizing the pulse width. We utilize a high-speed measurement setup to probe the energy consumption in PCM cells with varying pulse width (0.3 to 40 nanoseconds) and uncover the power dissipation dynamics. A key finding is that the switching power (P) remains unchanged for pulses wider than a short thermal time constant of the PCM ($\tau$$_t$$_h$ < 1 ns in 50 nm diameter device), resulting in a decrease of energy (E=P$\tau$) as the pulse width $\tau$ is reduced in that range. In other words, thermal confinement during short pulses is achieved by limiting the heat diffusion time. Our improved programming scheme reduces reset energy density below 0.1 nJ/$\mu$m$^2$, over an order of magnitude lower than state-of-the-art PCM, potentially changing the roadmap of future data storage technology and paving the way towards energy-efficient neuromorphic hardware

Semiconductors require stable doping for applications in transistors, optoelectronics, and thermoelectrics. However, this has been challenging for two-dimensional (2D) materials, where existing approaches are either incompatible with conventional semiconductor processing or introduce time-dependent, hysteretic behavior. Here we show that low temperature (< 200$^\circ$ C) sub-stoichiometric AlO$_x$ provides a stable n-doping layer for monolayer MoS$_2$, compatible with circuit integration. This approach achieves carrier densities > 2x10$^{13}$ 1/cm$^2$, sheet resistance as low as ~7 kOhm/sq, and good contact resistance ~480 Ohm.um in transistors from monolayer MoS$_2$ grown by chemical vapor deposition. We also reach record current density of nearly 700 uA/um (>110 MA/cm$^2$) in this three-atom-thick semiconductor while preserving transistor on/off current ratio > $10^6$. The maximum current is ultimately limited by self-heating and could exceed 1 mA/um with better device heat sinking. With their 0.1 nA/um off-current, such doped MoS$_2$ devices approach several low-power transistor metrics required by the international technology roadmap, Comment: To appear in ACS Nano (2021)

Metal contacts are a key limiter to the electronic performance of two-dimensional (2D) semiconductor devices. Here we present a comprehensive study of contact interfaces between seven metals (Y, Sc, Ag, Al, Ti, Au, Ni, with work functions from 3.1 to 5.2 eV) and monolayer MoS2 grown by chemical vapor deposition. We evaporate thin metal films onto MoS2 and study the interfaces by Raman spectroscopy, X-ray photoelectron spectroscopy, X-ray diffraction, transmission electron microscopy, and electrical characterization. We uncover that, 1) ultrathin oxidized Al dopes MoS2 n-type (> 2x10^12 1/cm^2) without degrading its mobility, 2) Ag, Au, and Ni deposition causes varying levels of damage to MoS2 (broadening Raman E' peak from <3 1/cm to >6 1/cm), and 3) Ti, Sc, and Y react with MoS2. Reactive metals must be avoided in contacts to monolayer MoS2, but control studies reveal the reaction is mostly limited to the top layer of multilayer films. Finally, we find that 4) thin metals do not significantly strain MoS2, as confirmed by X-ray diffraction. These are important findings for metal contacts to MoS2, and broadly applicable to many other 2D semiconductors.

Leakage currents through insulators received continuous attention for decades, owing to their importance for a wide range of technologies, and interest in their fundamental mechanisms. This work investigates the leakage currents through atomic layer deposited (ALD) $Al_2O_3$, grown on $SrTiO_3$. This combination is not only a key building block of oxide electronics, but also a clean system for studying the leakage mechanisms without interfacial layers that form on most of the conventional bottom electrodes. We show how tiny differences in the deposition process can have a dramatic effect on the leakage behavior. Detailed analysis of the leakage behavior rules out Fowler-Nordheim tunneling (FNT) and thermionic emission, and leaves the trap-related mechanisms of trap-assisted tunneling (TAT) and Poole-Frenkel as the likely mechanisms. After annealing the sample in air, the currents are reduced, which is ascribed to transition from trap-based mechanism to FNT, due to the elimination of the traps. The dramatic role of the assumptions regarding the flat-band voltage used for analysis is critically discussed, and the sensitivity of the extracted parameters on this magnitude is quantitatively described. We show that field effect devices based on structures similar to those described here, should be able to modulate $>10^{13} cm^{-2}$ electrons. These results provide general guidelines for reducing and analyzing leakage currents in insulators, and highlight some of the possible approaches and pitfalls in their analysis., Comment: 15 pages, 4 figures

Phase change memory (PCM) is an emerging data storage technology, however its programming is thermal in nature and typically not energy-efficient. Here we reduce the switching power of PCM through the combined approaches of filamentary contacts and thermal confinement. The filamentary contact is formed through an oxidized TiN layer on the bottom electrode, and thermal confinement is achieved using a monolayer semiconductor interface, three-atom thick MoS2. The former reduces the switching volume of the phase change material and yields a 70% reduction in reset current versus typical 150 nm diameter mushroom cells. The enhanced thermal confinement achieved with the ultra-thin (~6 {\AA}) MoS2 yields an additional 30% reduction in switching current and power. We also use detailed simulations to show that further tailoring the electrical and thermal interfaces of such PCM cells toward their fundamental limits could lead up to a six-fold benefit in power efficiency.

Step junctions are often present in layered materials, i.e. where single-layer regions meet multi-layer regions, yet their effect on thermal transport is not understood to date. Here, we measure heat flow across graphene junctions (GJs) from monolayer to bilayer graphene, as well as bilayer to four-layer graphene for the first time, in both heat flow directions. The thermal conductance of the monolayer-bilayer GJ device ranges from ~0.5 to 9.1x10^8 Wm-2K-1 between 50 K to 300 K. Atomistic simulations of such GJ device reveal that graphene layers are relatively decoupled, and the low thermal conductance of the device is determined by the resistance between the two dis-tinct graphene layers. In these conditions the junction plays a negligible effect. To prove that the decoupling between layers controls thermal transport in the junction, the heat flow in both directions was measured, showing no evidence of thermal asymmetry or rectification (within experimental error bars). For large-area graphene applications, this signifies that small bilayer (or multilayer) islands have little or no contribution to overall thermal transport.

The electrical and thermal behavior of nanoscale devices based on two-dimensional (2D) materials is often limited by their contacts and interfaces. Here we report the temperature-dependent thermal boundary conductance (TBC) of monolayer MoS$_2$ with AlN and SiO$_2$, using Raman thermometry with laser-induced heating. The temperature-dependent optical absorption of the 2D material is crucial in such experiments, which we characterize here for the first time above room temperature. We obtain TBC ~ 15 MWm$^-$$^2$K$^-$$^1$ near room temperature, increasing as ~ T$^0$$^.$$^6$$^5$ in the range 300 - 600 K. The similar TBC of MoS$_2$ with the two substrates indicates that MoS$_2$ is the "softer" material with weaker phonon irradiance, and the relatively low TBC signifies that such interfaces present a key bottleneck in energy dissipation from 2D devices. Our approach is needed to correctly perform Raman thermometry of 2D materials, and our findings are key for understanding energy coupling at the nanoscale.

The operation of resistive and phase-change memory (RRAM and PCM) is controlled by highly localized self-heating effects, yet detailed studies of their temperature are rare due to challenges of nanoscale thermometry. Here we show that the combination of Raman thermometry and scanning thermal microscopy (SThM) can enable such measurements with high spatial resolution. We report temperature-dependent Raman spectra of HfO$_2$, TiO$_2$ and Ge$_2$Sb$_2$Te$_5$ (GST) films, and demonstrate direct measurements of temperature profiles in lateral PCM devices. Our measurements reveal that electrical and thermal interfaces dominate the operation of such devices, uncovering a thermal boundary resistance of 30 m$^2$K$^{-1}$GW$^{-1}$ at GST-SiO$_2$ interfaces and an effective thermopower 350 $\mu$V/K at GST-Pt interfaces. We also discuss possible pathways to apply Raman thermometry and SThM techniques to nanoscale and vertical resistive memory devices.

The advancement of nanoscale electronics has been limited by energy dissipation challenges for over a decade. Such limitations could be particularly severe for two-dimensional (2D) semiconductors integrated with flexible substrates or multi-layered processors, both being critical thermal bottlenecks. To shed light into fundamental aspects of this problem, here we report the first direct measurement of spatially resolved temperature in functioning 2D monolayer MoS$_2$ transistors. Using Raman thermometry we simultaneously obtain temperature maps of the device channel and its substrate. This differential measurement reveals the thermal boundary conductance (TBC) of the MoS$_2$ interface (14 $\pm$ 4 MWm$^-$$^2$K$^-$$^1$) is an order magnitude larger than previously thought, yet near the low end of known solid-solid interfaces. Our study also reveals unexpected insight into non-uniformities of the MoS$_2$ transistors (small bilayer regions), which do not cause significant self-heating, suggesting that such semiconductors are less sensitive to inhomogeneity than expected. These results provide key insights into energy dissipation of 2D semiconductors and pave the way for the future design of energy-efficient 2D electronics.

Bardeen's model for the non-ideal metal-semiconductor interface was applied to metal-wrapped cylindrical nanowire systems; a significant effect of the nanowire diameter on the non-ideal Schottky barrier height was found. The calculations were performed by solving Poisson's equation in the nanowire, self-consistently with the constraints set by the non-ideal interface conditions; in these calculations the barrier height is obtained from the solution, and it is not a boundary condition for Poisson's equation. The main finding is that thin nanowires are expected to have tens of meV higher Schottky barriers compared to their thicker counterparts. What lies behind this effect is the electrostatic properties of metal-wrapped nanowires; in particular, since depletion charge is reduced with nanowire radius, the potential drop on the interfacial layer, is reduced - leading to the increase of the barrier height with nanowire radius reduction., Comment: 12 pages, 4 figures