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Abstract In this work, multi-level storage in the via RRAM has been first time reported and demonstrated with the standard FinFET CMOS logic process. Multi-level states in via RRAM are achieved by controlling the current compliance during set operations. The new current compliance setting circuits are proposed to ensure stable resistance control when one considers cells under the process variation effect. The improved stability and tightened distributions on its multi-level states on via RRAM have been successfully demonstrated.

A top‐down transfer process is developed via a rolling process associated with thermal release tape/poly(methyl methacrylate) (PMMA) bi‐supporting layers to realize large‐scale transfer processes on transition metal dichalcogenide materials. A 2‐inch MoS2 thin film transferred on SiO2/Si substrates with high integrity and a yield of ≈99% can be successfully achieved via the proposed process. MoS2‐based transistors with a transferred Au thin film as the contact electrode indicate a lower contact resistance of 8.4 kΩ with improved mobility and a higher on/off ratio compared with that of the MoS2‐based transistors with the evaporated Au thin film as the contact electrode. By applying the difference in adhesion force between metal oxides and metal on MoS2 and PMMA surfaces, the selective transfer of MoS2 films can be demonstrated. Furthermore, all‐transferred MoS2‐based transistor arrays are demonstrated by combining the selectively transferred MoS2 film as the channel material and the transferred Au thin films as the contact electrode, which results in uniform electrical properties featuring a carrier mobility of 10.45 cm2 V−1 s−1, a subthreshold swing of 203.94 mV dec−1, a normalized Ion of 8.3 μA μm−1, and an on/off ratio of 105.

Abstract An on-wafer micro-detector for in situ EUV (wavelength of 13.5 nm) detection featuring FinFET CMOS compatibility, 1 T pixel and battery-less sensing is demonstrated. Moreover, the detection results can be written in the in-pixel storage node for days, enabling off-line and non-destructive reading. The high spatial resolution micro-detectors can be used to extract the actual parameters of the incident EUV on wafers, including light intensity, exposure time and energy, key to optimization of lithographic processes in 5 nm FinFET technology and beyond.

Abstract This work proposed a modified plasma induced charging (PID) detector to widen the detection range, for monitoring the possible plasma damage across a wafer during advanced CMOS BEOL processes. New antenna designs for plasma induced damage patterns with extended capacitors are investigated. By adapting the novel PID detectors, the maximum charging levels of the detectors have been enhanced.

Abstract As one of the most promising embedded non-volatile storage solutions for advanced CMOS modules, resistive random access memory’s (RRAM) applications depend highly on its cyclability. Through detailed analysis, links have been found between noise types, filament configurations and the occurrence of reset failure during cycling test. In addition, a recovery treatment is demonstrated to restore the cyclability of RRAM. An early detection circuit for vulnerable cells in an array is also proposed for further improving the overall endurance of an RRAM array. Lifetime of RRAM can be extended to over 10 k cycles without fail bits in an array.

Abstract A novel in situ imaging solution and detectors array for the focused electron beam (e-beam) are the first time proposed and demonstrated. The proposed in-tool, on-wafer e-beam detectors array features full FinFET CMOS logic compatibility, compact 2 T pixel structure, fast response, high responsivity, and wide dynamic range. The e-beam imaging pattern and detection results can be further stored in the sensing/storage node without external power supply, enabling off-line electrical reading, which can be used to rapidly provide timely feedback of the key parameters of the e-beam on the projected wafers, including dosage, accelerating energy, and intensity distributions.

Abstract High-density interconnects, enabled by advanced CMOS Cu BEOL technologies, lead to closely placed metals layers. High-aspect ratio metal lines require extensive plasma etching processes, which may cause reliability concerns on inter metal dielectric (IMD) layers. This study presents newly proposed test patterns for evaluating the effect of plasma-induced charging effect on the integrity of IMD between closely placed metal lines. Strong correlations between the plasma charging intensities and damages found in IMD layers are found and analyzed comprehensively.

A new self-converging programming characteristic in a single-poly floating-gate memory cell with full-compatibility to a CMOS logic technology is observed and studied. A uniquely design cell with a narrow-bridging line between two coupling capacitors promotes a localized charging effect at the electron tunneling site, leading to clamping of threshold voltage states. Through this mechanism, the new multi time programmable (MTP) cells exhibit tight threshold voltage distributions for multi-level cells (MLC) operations. Improved cycling reliability and one-shot multi-level programming has been fully demonstrated in this work.

Fast and stable switching between states is one of the key factors for the success resistive random access memory (RRAM) development. In an array, wide reset efficiency variation in RRAM cells is found to link to the characteristics of its low frequency noise (LFN) in bit-cell current. Through Monte Carlo simulation on randomly placing conductive filaments (CF), LFN characteristics correspond to the densities of the CF in the RRAM film. Further correlations between LFN features and the reset efficiency are found. In addition, CF topography are found to change after long term cycling tests. A trimming process is proposed to minimize the impacts of stochastic CF generation, leading to increase reset speed.

Abstract In this work, an observation on random telegraph noise (RTN) signal in the read current of a FinFET dielectric RRAM (FIND RRAM) device is presented. The RTN signal of a FIND RRAM cell is found to change after the device being subjected to cycling stress. After undergoing cycling stress, RRAM cells have a stronger tendency to show more frequent and intense RTN signals. The increase of noise levels in FIND RRAM cells can be alleviated generally by high temperature anneal, and with this concept, an on chip annealing scheme is proposed and demonstrated.

Abstract Variability in resistive random access memory cell has been one of the critical challenges for the development of high-density RRAM arrays. While the sources of variability during resistive switching vary for different transition metal oxide films, the stochastic oxygen vacancy generation/recombination is generally believed to be the dominant cause. Through analyzing experimental data, a stochastic model which links the subsequent switching characteristics with its initial states of contact RRAM cells is established. By combining a conduction network model and the trap-assisted tunneling mechanism, the impacts of concentration and distribution of intrinsic oxygen vacancies in RRAM dielectric film are demonstrated with Monte Carlo Simulation. The measurement data on contact RRAM arrays agree well with characteristics projected by the model based on the presence of randomly distributed intrinsic vacancies. A strong correlation between forming characteristics and initial states is verified, which links forming behaviors to preforming oxygen vacancies. This study provides a comprehensive understanding of variability sources in contact RRAM devices and a reset training scheme to reduce the variability behavior in the subsequent RRAM states.

Plasma induced damage remains a critical concern in VLSI manufacturing process as a result of the introduction of the high-k and low-k dielectric layers and complicated 3D structures in advanced technology nodes. In this paper, the level of plasma induced charging distribution on a wafer is studied comprehensively. A strong correlation between the charging level and the geometry as well as densities ratio of via structures in dual damascene BEOL copper processes is found. In addition, the effect of plasma charging on Cu corrosion is studied in this paper. To investigate the root causes of such failure mode, an in-situ plasma charging recorder is embedded with RC test structures formed by Cu BEOL processes. The recorded charging current has a strong effect on the reliability levels of the via-chain resistors and backend capacitors. Experimental data suggests that plasma charging effect not only leads to gate dielectric stress on transistors but also affects the reliability performances of the copper interconnects.

Abstract A novel device for monitoring plasma-induced damage in the back-end-of-line (BEOL) process with charge splitting capability is first-time proposed and demonstrated. This novel charge splitting in situ recorder (CSIR) can independently trace the amount and polarity of plasma charging effects during the manufacturing process of advanced fin field-effect transistor (FinFET) circuits. Not only does it reveal the real-time and in situ plasma charging levels on the antennas, but it also separates positive and negative charging effect and provides two independent readings. As CMOS technologies push for finer metal lines in the future, the new charge separation scheme provides a powerful tool for BEOL process optimization and further device reliability improvements.

Abstract This paper reports a novel full logic compatible 4T2R non-volatile static random access memory (nv-SRAM) featuring its self-inhibit data storing mechanism for in low-power/high-speed SRAM application. With compact cell area and full logic compatibility, this new nv-SRAM incorporates two STI-ReRAMs embedded inside the 4T SRAM. Data can be read/write through a cross-couple volatile structure for maintaining fast accessing speed. Data can be non-volatilely stored in new SRAM cell through a unique self-inhibit operation onto the resistive random access memory (RRAM) load, achieving zero static power during data hold.

Abstract A retention behavior model for self-rectifying TaO/HfO x - and TaO/AlO x -based resistive random-access memory (RRAM) is proposed. Trapping-type RRAM can have a high resistance state (HRS) and a low resistance state (LRS); the degradation in a LRS is usually more severe than that in a HRS, because the LRS during the SET process is limited by the internal resistor layer. However, if TaO/AlO x elements are stacked in layers, the LRS retention can be improved. The LRS retention time estimated by extrapolation method is more than 5 years at room temperature. Both TaO/HfO x - and TaO/AlO x -based RRAM structures have the same capping layer of TaO, and the activation energy levels of both types of structures are 0.38 eV. Moreover, the additional AlO x switching layer of a TaO/AlO x structure creates a higher O diffusion barrier that can substantially enhance retention, and the TaO/AlO x structure also shows a quite stable LRS under biased conditions.

A new self-rectifying twin-bit RRAM in a novel 3-D interweaved cross-point array has been proposed and demonstrated in 28-nm high-k metal gate CMOS back end of line (BEOL) process. This high density of array architecture with the cell size only 70 × 100 × 187 nm can be manufactured without additional mask or process. The RRAM film is formed by via plug over shifting between two metal lines in back-end process with TaN/TaOxN RRAMs on both sides of a single via. The BEOL RRAM shows large read window between states. Fast switching time of 1 us for set operation and 10 us for reset was demonstrated. Excellent selectivity by its asymmetric IV characteristic enables the twin-bit 1R cells to be efficiently stacked in 3-D cross-point arrays without select transistors.

A new on-chip recovery operation is proposed in the self-aligned nitride (SAN) cell. Merged nitride spacer is sandwiched between high-k metal gate stacks in nano-meter CMOS process. The scaled gate length enables the SAN cell be erased by band-to-band hot hole. For multiple-time-programming operation, two effective recovery methods are proposed to recover on/off window after cycling stress. Both ac and dc methods are applied to eliminate deep-trapped charges via electrical self-heating. Experimental data demonstrates dc recovery methods that provide nearly full damage anneal capability and, in turn, effectively extend SAN cell's endurance level.

In this paper, a fully logic compatible via diode is developed for high-density resistive random access memory (RRAM) array applications. This novel via diode is realized by advanced 28nm CMOS technology with Cu damascene via. The device is stacked between a top Cu via and a bottom Cu metal with a composite layer of TaN/TaON based dielectric film. An asymmetric current-voltage characteristic in this MIM structure provides a forward/reverse current ratio up to 106. In a cross-point RRAM array, the suppression of sneak current path by incorporating this via diode enables array size to be greatly expended. Via diode provides an excellent solution for high-density embedded nonvolatile memory applications in the nano-scale CMOS technology.

In this work, we present a novel pH sensor using efficient laterally coupled structure enabled by Complementary Metal-Oxide Semiconductor (CMOS) Fin Field-Effect Transistor (FinFET) processes. This new sensor features adjustable sensitivity, wide sensing range, multi-pad sensing capability and compatibility to advanced CMOS technologies. With a self-balanced readout scheme and proposed corresponding circuit, the proposed sensor is found to be easily embedded into integrated circuits (ICs) and expanded into sensors array. To ensure the robustness of this new device, the transient response and noise analysis are performed. In addition, an embedded calibration operation scheme is implemented to prevent the proposed sensing device from the background offset from process variation, providing reliable and stable sensing results.

Correction In the original publication [1] Fig. 3 was presented incorrect. The correct additional file has been included with this erratum and the original article has been updated to rectify this error.