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The subset sum problem is a typical NP-complete problem that is hard to solve efficiently in time due to the intrinsic superpolynomial-scaling property. Increasing the problem size results in a vast amount of time consuming in conventionally available computers. Photons possess the unique features of extremely high propagation speed, weak interaction with environment and low detectable energy level, therefore can be a promising candidate to meet the challenge by constructing an a photonic computer computer. However, most of optical computing schemes, like Fourier transformation, require very high operation precision and are hard to scale up. Here, we present a chip built-in photonic computer to efficiently solve the subset sum problem. We successfully map the problem into a waveguide network in three dimensions by using femtosecond laser direct writing technique. We show that the photons are able to sufficiently dissipate into the networks and search all the possible paths for solutions in parallel. In the case of successive primes the proposed approach exhibits a dominant superiority in time consumption even compared with supercomputers. Our results confirm the ability of light to realize a complicated computational function that is intractable with conventional computers, and suggest the subset sum problem as a good benchmarking platform for the race between photonic and conventional computers on the way towards "photonic supremacy"., Comment: 13 pages, 6 figures

The implementation of quantum information technologies requires the development of integrated quantum chips. Femtosecond laser direct writing (FLDW) waveguides and superconducting nanowire single-photon detectors (SNSPDs) have been widely applied in integrated quantum photonic circuits. In this work, a novel FLDW waveguide-coupled SNSPD was designed and realized by integrating FLDW waveguides and conventional SNSPDs together. Through a COMSOL simulation, a waveguide end face-nanowire optical coupling structure was designed and verified. The simulation results showed that the FLDW waveguide-coupled SNSPD device, which had a target wavelength of 780 nm, can achieve 87% optical absorption. Then the preparation process of the FLDW waveguide-coupled SNSPD device was developed, and the fabricated device achieved a system detection efficiency of 1.7% at 10 Hz dark count rate. Overall, this method provides a feasible single-photon detector solution for future on-chip integrated quantum photonic experiments and applications.

The data/timing formatter is a key module in automatic electronics test equipment; it formats the test data to the desired wave shape and places the timing edges at the designated locations. In this work, we investigate the design and implementation of the FPGA-based data/timing formatter. Compared to its ASIC counterpart, the FPGA-based formatter is more flexible because it can be reconfigured to best fit the target test specifications. However, routing uncertainty and limited types of available logic and interconnect resources also pose great challenges. This work proposes a formatter design that is suitable for FPGA implementation. Several high-linearity FPGA-based programmable delay lines are developed. According to its characteristics, each type of delay lines is assigned a different role in the formatter. The formatter is also equipped with a calibration unit to further improve the edge placement resolution and accuracy. A 100-Msps FPGA-based data/timing formatter with 20-ps edge placement resolution has been implemented on an FPGA development board to validate our ideas.

Loopback testing is a powerful technique for testing the analog-to-digital converter (ADC) and digital-to-analog converter (DAC) pair embedded in a mixed-signal system-on-chip (SoC). While attractive, its performance is generally limited by the achievable test resolution and the potential fault masking problem. In this work, a loopback linearity testing technique for an ADC/DAC pair is presented; the key idea is to raise the effective ADC and DAC resolution by scaling the DAC output. First, during ADC testing, we scale down the DAC output to achieve the required test stimulus resolution and adjust the DAC output offset to cover the ADC full-scale range. Then, for DAC testing, we raise the effective ADC resolution by scaling up the DAC output. Both simulation and measurement results are presented to validate the proposed technique.

The programmable delay line is one of the key components in automatic test equipment. Recently, implementation of programmable delay lines on FPGAs has drawn growing attention due to the flexibility and reconfiguration capability that FPGAs provide. In this work, we propose the subset sum delay line (SSDL) architecture for FPGA-based delay lines. The SSDL architecture takes advantage of the inevitable FPGA process variations, structure irregularities and routing uncertainties to realize high-quality FPGA-based delay lines. Furthermore, compared to previous FPGA-based delay lines, the SSDL architecture is FPGA independent, this substantially enhances its portability across different FPGA generations and suppliers. An SSDL is realized on Alter a Cyclone II FPGA. Measurement results show that it achieves 76 ps resolution and has a dynamic range of 32 ns.

In this paper, a bit weight extraction technique is proposed to test and calibrate the successive approximation register (SAR) analog-to-digital converter (ADC). The proposed technique is based on major carrier transition (MCT) testing, the MCTs are generated through simple capacitor switching and then measured by the embedded comparator and a coarse design-for-test (DfT) digital-to-analog converter (DAC) that couples to the capacitor DAC (CDAC). From the results, the individual bit weights are extracted and the ADC performance can thus be estimated and calibrated. Simulation results show very high test accuracy and linearity improvement can be achieved by the proposed technique.

Capacitor mismatch is the linearity limiter of charge redistribution SAR ADCs. This paper aims at detecting and removing the mismatch induced missing-decision levels (MDLs), i.e., large positive DNLs; these errors lead to information loss that cannot be recovered by external calibration. A switched-capacitor based approach is proposed to avoid DC currents and reduce design overhead; the hardware modification also supports comparator offset compensation to improve calibration quality. Simulation results show that the proposed technique effectively improves the SAR ADC linearity in the presence of capacitor mismatch and comparator offset.

This paper presents pre/post-bond testing and calibration techniques for the successive approximation register (SAR) analog-to-digital converter (ADC) array in a three-dimensional (3-D) CMOS imager. The underlying idea is to test and calibrate the SAR ADC by measuring the major carrier transitions (MCTs) of its digital-to-analog converter (DAC) capacitor array (C-Array). During the pre-bond stage, when access to the die is very limited, we propose a calibration-oriented testing technique that only determines whether the ADC array can achieve the desired performance after calibration. Then, during the post-bond stage, we utilize the digital resources from the image signal processor (ISP) die to perform more thorough characterization and calibration of the ADC array. Simulation results are presented to validate the proposed techniques.

This paper presents a low-cost pre- and post-bond self-testing and calibration methodology for the successive approximation register (SAR) analog-to-digital converter (ADC) array in a three-dimensional (3-D) CMOS imager. The basic idea is to test and calibrate the SAR ADC by measuring the major carrier transitions (MCTs) of the internal digital-to-analog converter (DAC) capacitor array. During the pre-bond stage, when access to the die is very limited, we propose a calibration-oriented testing technique that only determines whether the ADC array can achieve the desired performance after calibration. This substantially reduces the required design-for-test (DfT) circuitry complexity and test time. Then, during the post-bond stage, more thorough characterization on the ADC array is performed, we utilize digital resources from the image signal processor (ISP) die to analyze the measurement results, compute the calibration parameters, and perform the digital calibration. Simulation results are presented to validate the proposed techniques.

For embedded analog-to-digital converters (ADCs) fabricated with deep sub-micron technology, calibration has become mandatory to ensure acceptable yield against process variations. This paper presents a pipelined ADC calibration technique that targets the capacitor mismatch and comparator offset associated with the pipelined ADC stages. The calibration technique is self-testing assisted; it utilizes the built-in histogram testing circuitry to (1) obtain the necessary calibration information, and (2) validate the calibrated ADC. Simulation results show that the calibration strategy substantially enhances the ADC static linearity and dynamic performance.

In this paper, we present a histogram-based two-phase calibration technique for capacitor mismatch and comparator offset of 1-bit/stage pipelined Analog-to-Digital Converters (ADCs). In the first phase, it calibrates the missing decision levels by capacitor resizing. Unlike previous works which require large capacitor arrays, only few switches are added to the circuit. The second phase performs missing code elimination. It achieves better calibrated linearity and provides better mismatch tolerance than the traditional digital calibration technique. Simulation results show that the proposed technique effectively improves both the static and dynamic performance.

This paper presents a leakage characterization technique for switched capacitor (SC) integrators. It is a low-cost on-chip solution because (1) the test stimulus is a DC voltage whose exact value is not important, and (2) the output response digitizer is simply a comparator. Simulation results show that integrator leakage can be accurately characterized even in the presence of noise and comparator offset. Together with existing SC testing techniques, the leakage characterization technique helps better characterize SC circuits; its application to several popular SC circuits is demonstrated.

In this paper, we present an efficient calibration technique for 1-bit/stage pipelined analog-to-digital converters (ADCs). The proposed technique calibrates capacitor mismatch and comparator offset induced non-ideal ADC output behavior; it is a two-phase calibration scheme that relies on linear histogram testing to collect the required information. In the first phase, it calibrates the missing-decision-level errors by capacitor resizing. Unlike previous works which require large capacitor arrays, only few switches are added to the circuit. The second phase performs missing code elimination. It achieves better calibrated linearity and provides better mismatch tolerance than the traditional digital calibration technique. Simulation results show that the proposed technique effectively improves INL and DNL.

A novel micromotor is described, in which the gear-shaped pyrolytic graphite rotor is levitated, rotated and constrained by the combination of static magnetic, electrostatic forces and torques. Two concentric ring-shaped permanent magnets are presented, which are used for realising the static magnetic field. By the microelectromechanical systems process, the metal electrodes, pads and SU-8 column post were fabricated on the silicon substrate above the magnets. The stator was assembled by the silicon and the magnets. The three-phase axial variable-capacitance motor principle was applied for driving the rotor. The rotor is stably levitated to a height of about 0.70 mm over the magnets. When a 30 V driving voltage was added, the rotor speed was over 10 rpm in atmosphere.