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In this paper, a new bulk silicon isolation structure with wafer-thick trenches is proposed for automotive (42 V) power-integrated-circuit applications. This technology provides the advantages of complete isolation with lower wafer cost and higher thermal-dissipation capability as compared with the silicon-on-insulator technology. Experimental results show that the new isolation structure can provide complete electrical isolation and with a 13\% reduction in thermal resistance.

In recent years, polycrystalline silicon (polysilicon) thin film transistors (TFTs) have been actively investigated due to their relatively high field-effect mobility and high current driving ability. These characteristics allow them to find an increasing number of applications in the area of large area microelectronics, particularly for active-matrix liquid-crystal displays (AMLCDs) and active-matrix organic-light-emitting diodes (AMOLEDs). Low temperature polysilicon TFT appears to be one of the most promising technologies for display system-on-panel applications. For these applications, scaled-down poly-Si TFTs with high performance and high reliability are required. In order to build the integrated system on panels, a variety of devices such as high current digital devices, kink-free analog devices, high-voltage driver devices, capacitors, memory devices, etc., are needed. All of them should be available in low temperature poly-Si technology. In this thesis, novel poly-Si TFT devices and technologies are designed and implemented to meet the above requirements. First, a novel self-align ultra-thin elevated-channel CMOS poly-Si TFT (SA-UT- ECTFT) is presented. The structure makes use of a back-light exposure technique to implement a self-aligned channel structure, in which a thin channel region is used to achieve high on-current, and a thick source/drain region is used to reduce the lateral electric field, thereby suppressing the kink effect and minimizing the leakage current. Using this structure, TFT devices with good saturation characteristics, good breakdown characteristics, high on-current, and low leakage current, which are very attractive for use in both analog and digital application, were obtained. Moreover, it makes the process control and the scale-down of the devices to be easier. Second, a new CMOS self-aligned double-gate (SADG) poly-Si TFT is present. The self-alignment between the top- and bottom- gate is also realized by the back-light exposure te

In this letter, a, novel ultrathin vertical channel (UTVC) NMOSFET with asymmetric fully overlapped lightly doped drain (LDD) is proposed,and demonstrated using solid-phase epitaxy (SPE). A boron-doped polycrystalline Si0.5Ge0.5 gate was used to tune the threshold voltage, a lightly doped (<1 x 10(15) cm(-3)) channel was used to suppress the electron mobility degradation, and an asymmetric fully overlapped LDD was adopted to reduce the series resistance as compared to the conventional LDD. Devices with 50-nm channel length were achieved by using 15-nm ultrathin channel thickness, and they provided high current drive, steep subthreshold slope, and good V-T roll-off characteristics.