1. A 2GSPS 8-bit ADC with digital foreground calibration technology
- Author
-
Yong-Lu Wang, Xin-Fa Huang, and Zheng-Ping Zhang
- Subjects
Computer science ,business.industry ,Real-time computing ,Bandwidth (signal processing) ,8-bit ,Analog-to-digital converter ,Successive approximation ADC ,Folding (DSP implementation) ,Chip ,Multiplexing ,law.invention ,law ,Hardware_INTEGRATEDCIRCUITS ,Nyquist–Shannon sampling theorem ,business ,Computer hardware - Abstract
A high-speed 8-bit analog-to-digital converter in 0.35µm BiCMOS process technology is presented. The ADC uses the unique folding and interpolating architecture and the dual-channel timing interleave multiplexing technology to achieve a sampling rate of 2GSPS. In case of digital calibration, as a result of testing, the ADC achieves 7.32ENOB at analog input of 484MHz, and 7.1ENOB at Nyquist input after the chip is self-corrected.
- Published
- 2011