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Fine-grained task models can exploit parallelism to achieve high performance for multiprocessor system-on-chip (MPSoC). However, fine-grained models face the issues of high-communication overhead and difficult scheduling decisions, and the two challenges are inter-dependent. To address the issues, this paper gives a full analysis of the fine-grained communication optimization technique and communication pipeline, from both time and topology perspectives, and proposes a static fine-grained communication-aware task scheduling (FCATS) approach, which integrates scheduling with communication pipeline for acyclic and cyclic applications based on the fine-grained Simulink model. The approach contains search-based scheduling with high-quality solutions utilizing genetic algorithm-integer linear programming (GA-ILP) and hybrid GA-heuristic scheduling with short solving time to meet different demands for users. The experimental results with both synthetic and real-life benchmarks on the 4/8/16-CPU platform demonstrate the efficiency of the approach on performance improvements compared to previous works.

Fine-grained multithreaded models can provide more opportunities for system performance improvements, but they face large amount of communication overhead. To reduce the communication overhead to improve performance, message aggregation and communication pipeline have been proposed and their advantages have been discussed in previous works. However, when exploiting them in reallife applications, it is challenging to maximize their advantages due to their unrevealed problems. This paper investigates the two communication optimization techniques from the view of their problems to fulfill the studies. We have found that when applying the techniques, message aggregation may have the deadlock problem and latency problem, and communication pipeline may face the ineffective problem and prolog and epilog problem. Based on the basic requirement of allocating the two techniques on an initial schedule, we then present general solutions to avoid or handle the problems. To obtain a minimum schedule length for an initial schedule, we further develop a binary particle swarm optimization-based finegrained communication optimization method to allocate message aggregation and communication pipeline for best performance. The method is also integrated into light and efficient simulink compiler for embedded application multithreaded code generator to generate high quality codes. Experimental results on both synthetic and real-life applications demonstrate the efficiency of the proposed method.

Energy saving and system reliability are two crucial issues for designing modern multiprocessor systems. There has been reliability-aware power management with dynamic voltage-frequency scaling (DVFS) schemes in recent studies. However, they are limited to optimization under the impact of DVFS on energy and reliability and have not considered reducing the non-negligible leakage energy consumption. In this paper, we focus on co-management of system reliability and total energy for applications with precedence constrained tasks on heterogeneous multiprocessor real-time systems. We first investigate the impact of energy management techniques on both reliability and energy of the systems using task recovery for fault tolerance and then propose an Energy-efficient Fault-tolerant Scheduling (EFS) scheme integrated with power mode management, which can mitigate the negative impact of DVFS on system reliability. To obtain the optimal energy-efficient reliability-guaranteed scheduling for pre-mapped applications on systems considering various realistic issues, we build mixed integer linear programing formulations with the proposed EFS scheme. To address mapping and scheduling for energy-efficiency and fault-tolerance, we finally develop a framework implemented by a List-based Binary Particle Swarm Optimization algorithm. The extensive comparative evaluations for synthetic and realistic benchmarks show that our approaches outperform several related studies in terms of energy consumption and system reliability.

Functional verification has become one of the main bottlenecks in the cost-effective design of embedded systems, particularly for symmetric multiprocessors. It is estimated that verification in its entirety accounts for up to 60% of design resources, including duration, computer resources, and total personnel. Simulation-based verification is a long-standing approach used to locate design errors in the symmetric multiprocessor verification. The greatest challenge of simulation-based verification is the creation of the reference model of the symmetric multiprocessor. In this paper, we propose an efficient symmetric multiprocessor reference model, Hybrid Model, written with SystemC. SystemC can provide a high-level simulation environment and is faster than the traditional hardware description languages. Hybrid Model has been implemented in an efficient 32-bit symmetric multiprocessor verification. Experimental results show our proposed model is a fast, accurate, and efficient symmetric multiprocessor reference model and it is able to help designers to locate design errors easily and accurately.