1. CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology
- Author
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Henry H. Radamson, Yuanhao Miao, Ziwei Zhou, Zhenhua Wu, Zhenzhen Kong, Jianfeng Gao, Hong Yang, Yuhui Ren, Yongkui Zhang, Jiangliu Shi, Jinjuan Xiang, Hushan Cui, Bin Lu, Junjie Li, Jinbiao Liu, Hongxiao Lin, Haoqing Xu, Mengfan Li, Jiaji Cao, Chuangqi He, Xiangyan Duan, Xuewei Zhao, Jiale Su, Yong Du, Jiahan Yu, Yuanyuan Wu, Miao Jiang, Di Liang, Ben Li, Yan Dong, and Guilei Wang
- Subjects
CMOS ,process integration ,nanoscale transistors ,FDSOI ,GAA ,TFET ,Chemistry ,QD1-999 - Abstract
After more than five decades, Moore’s Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D transistors in the form of gate-all-around (GAA) transistors are being considered as an excellent solution to scaling down beyond the 5 nm technology node, which solves the difficulties of carrier transport in the channel region which are mainly rooted in short channel effects (SCEs). In parallel to Moore, during the last two decades, transistors with a fully depleted SOI (FDSOI) design have also been processed for low-power electronics. Among all the possible designs, there are also tunneling field-effect transistors (TFETs), which offer very low power consumption and decent electrical characteristics. This review article presents new transistor designs, along with the integration of electronics and photonics, simulation methods, and continuation of CMOS process technology to the 5 nm technology node and beyond. The content highlights the innovative methods, challenges, and difficulties in device processing and design, as well as how to apply suitable metrology techniques as a tool to find out the imperfections and lattice distortions, strain status, and composition in the device structures.
- Published
- 2024
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