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This paper reports the etching process of fused silica by inductively coupled plasmas (ICP) for through glass via (TGV) applications. Mixed C4F8 and Ar were used as etching gases in present experiments. The effects of key factors, including etching gases, chamber pressure and substrate temperatures, on etch rate and via profile were studied. Results showed that a high etch rate of about 0.75 μm/min with smooth and vertical sidewall of TGVs can be obtained. Compared to Ar flux and chamber pressure, the effect of C4F8 flux on etch rate is more remarkable. Vertical vias (>89°) can be achieved by increasing the substrate temperature and decreasing the mixing ratio of C4F8 and Ar. Besides, micro-pillars at the bottom of via were observed when the substrate temperature was set at 0 °C. As the substrate temperature reached to 80 °C, micro-pillars were removed clearly. Optimized results indicate that the ICP etching is an effective method for fabricating TGV.

3D integration requires vertical stacking of dies while forming permanent electrical and mechanical connections between the input/output pins of the devices. Through silicon via (TSV) is one of the key elements for 3D integration. This paper presents different liner and barrier/seed approaches for realizing 10×100µm void-free copper filled TSVs. It is found that the plasma enhanced chemical vapor deposition (PECVD) TEOS film shows high dielectric constant, high leakage current and low step coverage. The thermal oxide film offers near 100% step coverage and low leakage current, but the growth rate is very slow. Hence a thermal oxide/PECVD TEOS bi-layer is formed to combine the advantage of each layer. Apart from the conventional plasma vapor deposition (PVD) barrier/seed, a novel metallization scheme with an atomic layer deposition (ALD) barrier and electroless deposited (ELD) seed is also investigated, which shows big potential for further scaling up the aspect ratio of TSV. Finally, a silicon interposer with thousands of TSVs is fabricated and 2.5D integration of device chips is demonstrated, from which good eye diagram is observed. Display Omitted

Stacking of ICs using three-dimensional (3D) integration technology helps in significantly reducing wiring lengths, interconnection latency, and power dissipation while enhancing performance. Through silicon vias (TSVs) are regarded as a key enabling technology for 3D IC integration which assists in the realization of highly miniaturized and complex next-generation systems. Due to the thermal expansion (CTE) mismatch between copper and silicon, the copper in silicon vias tends to pump up as a result of thermal-mechanical stress during the post fabrication processes and/or during the lifetime of chip usage. One way to minimize or get rid of copper pumping is through heat treatment, for instance annealing or aging. The TSV wafers could be annealed right after copper plating process, or after chemical mechanical polish (CMP) process, or both. The residual stress might be thoroughly released by repeating annealing and CMP processes several times, however, the cost for fabricating the TSVs is increasing drastically, which is mainly attributed to the use of expensive CMP. To lower down the cost and minimize the CMP steps is one of the concerns from industry. In this paper, we report the thermal mechanical assessment of Cu pumping treated at different annealing conditions. moreover, the impact of different integration approaches on the TSV pumping behavior is also investigated. The finite element analysis method, ANSYS, is used to model and simulate the copper pumping at different temperatures, as shown in Fig.1. The pumping is measured by optical profiler, BRUKER ContourGT-X3, as shown in Fig.2. It has been found out that the copper grain size increases with annealing temperature, which is potentially contributed to larger protrusion. The preliminary results show that the annealing after copper plating process affects the microstructure evolution and pumping of TSVs. Figure 1

Through glass via (TGV) technology is considered to be a cost effective enabler for the integration of micro electromechanical systems and radio frequency devices. Inductively coupled plasma and Bosch etching process comprise one of the most pervasive methods for through silicon via (TSV) formation. Unfortunately an equivalent process for glass etching remains elusive. In this paper, the influence of plasma etching for fused silica glass were investigated to find the best tradeoff between etch rate and profile of TGVs. The process parameters including bias power, gas flow rate, ratio of etching gases and reaction chamber pressure using Ar/C4F8 inductively coupled plasmas were studied. The etching results show that all these three parameters have a significant impact on the etch rate. Furthermore, the adjustment including total flow rate and ratio of Ar/C4F8 and chamber pressure can be used to control the via profile. Constant fused silica glass etch rate greater than 1 μm/min was obtained when chiller temperature was 40 °C with etching time of 60 min. The profile angle of TGVs with nearly 90° was also achieved.

Thermo-gravimetric analysis (TGA) was used to assess the thermal stability of a temporary adhesive. High temperature is one important factor leading to the voids formation in bonded wafers, which can degrade bonding force and cause chipping. Some heat treatment experiments were devised to investigate the influence of high temperature on the bonding quality. The prebake process before temporary bonding plays a very important role in preventing voids from forming between bonded wafers, which can be confirmed by the TGA results. A short loop evaluation was performed to assess the temporary bonding quality with different prebake and heat treatment temperatures. The results were used to optimize prebake conditions. Application to 2.5D through silicon vias temporary bonding and backside processing is demonstrated.

The dielectric via liner of through silicon vias was deposited at 400 °C using a tetraethyl orthosilicate (TEOS)-based plasma enhanced chemical vapor deposition process in a via-middle integration scheme. The morphology, conformality and chemical compositions of the liner film were characterized using field emission scanning electron microscopy and Fourier Transform Infrared spectroscopy. The thermal properties and electrical performance of blanket TEOS films were investigated by high temperature film stress and mercury probe Capacitance–Voltage measurements. The TEOS SiO 2 films show good conformality, excellent densification, low thermal stress, high breakdown voltage and low current leakage.

In order to meet the need of high integration and low cost of wireless communication systems, passive devices are widely used in all kinds of systems. This paper introduces an innovative method to manufacture integrated passive inductors based on glass reflow process. IPDs(integrated passive devices) have been simulated by 3D EM(electromagnetic) simulator software HFSS(high frequency structure simulator). From 0GHz to 10GHz, the Q value is above 200, higher than the Q value of conventional thin film inductors. Moreover, several key parameters of spiral inductors including inductor diameter, inductor thickness, substrate thickness, inductor width and inductor space are investigated. Finally, manufacturing process of inductors is presented.

Through silicon via (TSV) technology offers a promising approach to achieve three dimensional integrated circuit integration. Via-last TSV process has the advantages of flexibility and lower cost. In this paper, we report our latest progress on wafer level packaging by via-last process. The 200mm device wafer was bonded with a carrier wafer. Then, the vertical TSV structure with aspect ratio of 3∶1 was realized from the device wafer side. The silicon vias are insulated by low temperature PECVD silicon dioxide. All the process steps are obtained at the wafer level using the state-of-the-art facilities. Detailed considerations in the process are introduced. Dielectrics etching without photoresist protection is used. Two plating mechanisms are utilized to achieve a robust TSV structure. The via-last process provides a cost-effective solution for heterogeneous 3D integration.

MEMS devices are continuous evolving to achieve smaller size and lower cost with improved performance. The Through silicon via (TSV) technology offers a promising approach from the perspective of MEMS device packaging and integration. In this paper, we report our latest progress on wafer level packaging of MEMS devices by via-last process. The 200mm MEMS wafer was bonded with a glass cap wafer. Then, the vertical TSV structure with aspect ratio of 3:1 was realized from the device wafer side. The silicon vias are insulated by PECVD silicon dioxide. All the process steps are realized at the wafer level using the state-of-the-art facilities. The via-last integration, electrical test and reliability test are performed. The open/short electrical test results approve the principle, and the reliability test results further convince the developed via last process. This paper introduces a robust and cost-effective solution for heterogeneous 3D integration.

This paper presents a novel configuration consisting of a micromachined diaphragm and a standing beam for sensing airflow. A piezoelectric Pb(Zr,Ti)O3 (PZT) film is deposited by spin-coating on the diaphragm to actuate and sense the vibration at its resonant frequency. A standing and extruded beam built on the diaphragm responds to the aerodynamic drag force, inducing mechanical strain, increasing the stiffness of the structure, and subsequently shifting the resonant frequency. The finite element method is used to demonstrate the first four mode shapes and predict the frequency shift of the proposed structure when subjected to airflow. The prototype microstructure is fabricated by combining the PZT sol–gel process and silicon micromachining. In particular, a two-step deep silicon etching process is developed to form the diaphragm structure with a standing silicon beam on it. Flip-chip bonding by solder balls is adopted to electrically connect the electrode pads to the circuit board. The characterization of the flip-chip bonded sensor chip exhibits superior piezoelectric and electrical properties. The wind tunnel test shows a 25 Hz resonant frequency shift for a wind speed of 10 m/s.

Pressure influences on the vibration characteristics of piezoelectric circular microdiaphragm based pressure sensors are investigated theoretically and experimentally. It was demonstrated that only Bessel function of zero order, m = 0, participates in the vibration modes of the microdiaphragm symmetrically loaded by pressure. The piezoelectric circular microdiaphragm was fabricated by combining sol–gel PZT thin film and MEMS technology. A high value of pressure sensitivity, as high as 280 Hz/mbar, has been achieved; this value is 2.43 times higher than the currently reported sensitivity (i.e., 115 Hz/mbar) in the literature.

A novel micro CRLH (composite right/left-handed) wide band filter based on Left handed material (LHM) theory was designed and fabricated. As a promising design, the length of the main part is only 1/20 compared to the working wavelength. It can be used to eliminate the noise in RF interconnect and other area. The phase shift in LHM is negative. This characteristic can decrease the phase delay. And also, the absolute value of phase constant will increase when frequency decrease at the left handed band (LH-band), which contribute to minimize the design. The other advantage of the LHM is that the phase constant will changed to the opposite direction, when the wavelength changed with the working frequency. This provides a negative feedback to the electric length, so the left handed region has a wider band width. Measurements results show that relative bandwidth (3dB) of 8 cells is 71.42%. The relative bandwidth (3dB) of 4 cells is 58.46%.

Future microwave networks require miniature high-performance tunable elements such as switches, inductors, and capacitors. In this paper, high performance variable capacitor was fabricated by simple microelectromechanical systems (MEMS) technology. The capacitance and quality (Q) factor at 1 GHz are 0.792 pF and 51.6. The pull-in voltage is 13.5 V and the tuning ratio of the capacitor is more than 1.31:1. A reduced-order model for the dynamic characteristics of the capacitor is established based on the equilibrium among the plate flexibility.

The uniformity and deformation of electrochemical deposition (ECD) bumps get more and more important with the pitch shrinking and density increasing according to the requirement of modern electronic industry. In this paper, wafer level diameter and thickness distribution, surface roughness and hardness of Au bumps were characterized under different electroplating current densities and bath temperatures. Some valuable results were obtained. First, the diameter of ECD Au bumps was enlarged for 5-30 mu m at all positions on the wafer for both the bumps of 10-100 mu m diameters. Electroplated at 40 degrees C, the diameter distribution of Au bumps was similar to that of photoresist. While electroplated at 60 degrees C, its distribution was more symmetric. Second, more uniform thickness distribution of Au bumps was obtained when the bath temperature increased from 40 to 60 degrees C or the electroplating current density decreased from 8 to 3 mA/cm(2). Third, the Au bumps electroplated at 60 degrees C exhibited the surface roughness of 105-125 nm independent of electroplating current densities. The Au bumps electroplated at 40 degrees C exhibited the surface roughness of 40-45 nm for 3 mA/cm(2) and 5 mA/cm(2) and 923.45 nm for 8 mA/cm(2). Fourth, the hardness of Au bumps decreased with electroplating temperature increasing from 40 to 60 degrees C. The difference of hardness got at between 40 and 60 degrees C can be vanished by the following anneal process at 60 degrees C. In addition, the big differences among different current densities electroplated at 40 degrees C can also be vanished by the anneal process. Finally, possible reasons leading to above results were discussed.

Modeling, optimization and performance of on-chip solenoid inductors is presented. MATLAB is used to get the π-equivalent circuit model parameters. The effects of the geometrical parameters on the inductance and quality factor (Q-factor) are different. Normally, the performance of the inductors can be improved by increasing the coil turns in a way and increasing the length of the conductor, but both of them will occupy more chip area, which is not good for the minimization of the on-chip system. It is desirable to improve the performance of inductor by increasing the height of the via. Of the three types of fabricated inductors covering the same area, the inductors with the height of via 15, 30 and 45 μm have high performance. The self-resonant frequency is up to 10 GHz. The inductances and Q-factors at peak-Q frequency (about 5.8 GHz) are 1.16, 1.35, 1.78 nH and 21.9, 27, 38, respectively.

A novel method for fabrication of multi-layer microstructures of microelectro-mechanical system (MEMS) devices is described. This technique, which combines bulk silicon micromachining technique and UV-LIGA technique can overcome some shape limitations of single technique on complex microstructures. To demonstrate this combination, the SU-8 microstructure fabricated in the etched silicon grooves is presented. In this fabrication process, a SU-8 removal method by fuming sulfuric acid was introduced and a novel type of plastics PETG was tried in microhot embossing process. The proposed fabrication process can be applied to fabricating a high-aspect-ratio microstructure for a large displacement actuator and precision sensors. Moreover, this combined process enables the fabrication of more complex structures, which cannot be fabricated by bulk micromachining or UV-LIGA alone.

Through silicon via (TSV) based 2.5D and 3D integration technology is regarded as the most promising enabling technology for next generation system integration. One of the concerns associated with TSV is the reliability issue of the TSV based devices due to the CTE mismatch between silicon and copper. In this paper, we report the reliability assessment of Cu pumping treated at different annealing conditions. The pumping of TSVs having a diameter of 10 µm and a depth of 100 µm has been characterized by white light optical profiler. According to the TC, HTS and HAST test results, higher annealing temperature is beneficial to control the Cu pumping and improve the TSV reliability.

2.5D/3D integration has been attracting both academic and industry interests for extending the Moore's Low in recent years and several products using such technology have been emerged. This paper introduces the development progress of key process modules for 2.5D/3D IC integration on our 300mm platform. Experiment results for high aspect ratio TSV formation, fine-pitch RDL & bumping, low cost backside TSV revealing, and wafer level conductive bonding are given. The application of 2.5D/3D TSV integration is also discussed.

The microstructures of the TiC cermet/steel joint brazed with Ag–31Cu–23Zn brazing alloy (1123 K, 20 min) and Ag–54Cu–33Zn brazing alloy (1123 K, 20/25 min) were investigated. When the amounts of Cu and Zn increase in the brazing alloy, there are not many Cu–base solid solution stripes and blocks but few Cu–base solid solution blocks occurred in the middle of the brazing alloy.

Through silicon via (TSV) is regarded as one of the most advanced packaging technologies, however, many serious reliability issues need to be paid more concerns. The Cu pumping effect is one of the most crucial reliability problems. Due to different coefficient of thermal expansion for different packaging materials, CuTSV can deform and damage the wiring redistribution layers and degrade the reliability of the package as a whole during normal processing. Therefore, this work focuses on the influence which different thermal annealing processes have on Cu pumping in Cu-filled TSVs. Cu TSVs having 20μm in diameter and 120μm in depth were fabricated on 200 mm wafers by etching, insulation layer deposition, barrier layer deposition, seed layer deposition and Cu plating in sequence. Then the wafer surface was polished to remove the excessive Cu. Two anneal approaches were designed to investigate Cu TSV pumping. One was CMP first before annealing, and the other was annealing before CMP and followed by the 2nd annealing. Anneal tests were done in a nitrogen environment to protect Cu from oxidation. The annealing temperatures were set at 300 o C and 400 o C with a dwell time of 40min. The degree of pumping was evaluated by measuring the height and volume profiles before and after annealing by using a white light interferometer. Results show that the Cu TSV increased by 0.105μm and 0.168μm in height and 90.443μm 3 and 93.993μm 3 in volume at 300 o C and 400 o C with CMP first approach. However, the Cu TSV increased by only 0.066μm and 0.075μm and 30.797μm 3 and 10.077μm 3 in volume at 300 o C and 400 o C with anneal first approach. It can be concluded that the Cu pumping effect may be restrained by anneal first approach.

Temporary bonding and release processes are regarded as the critical technologies in 2.5D and 3D IC integration. The process is especially challenging when the device contains high topography structures like copper pillar bumps. This paper presents the results of simulation, bumping process, wafer temporary bonding, thinning and debonding. Through careful consideration and optimization of the above mentioned aspects, TSV wafers with 30 μm copper pillar bumps can be successfully released using the thermal-sliding debonding mechanism.

TSV (through-silicon-via) has been regarded as a key technology for 2.5D and 3D electronic packaging. However, the manufacturing of the through silicon interposer (TSI) is very challenging and costly. The minimization of the warpage of the TSV interposer wafer is crucial for successful subsequent processing, for example, thin wafer handling, backside via revealing and copper pillar bumping. In this paper, warpage was tested before and after most of the backside process steps. Wafer level warpage modeling methodology has been developed by finite element analysis (FEA) using equivalent material model. The warpage was simulated and analyzed by considering different process factors.

Through glass via (TGV) technology is considered to be a cost effective enabler for micro electromechanical systems (MEMS) and radio frequency (RF) system-in-package (SIP) technology. Inductively coupled plasma (ICP) and the Bosch etching process comprise one of the most pervasive methods for via formation in silicon. Unfortunately an equivalently process for glass remains elusive. In this paper, the influences of three process parameters, bias power, argon (Ar) flow rate and substrate temperature, on fused silica glass etching in Ar/C 4 F 8 inductively coupled plasmas was investigated. High glass etching rate more than lμm/min was obtained when chiller temperature was fixed at 40 °C. The results show that bias power and temperature have a significant impact on the etch rate and that the flow rate and ratio of Ar/C 4 F 8 can be used to control the via profile.

Through silicon vias (TSVs) are regarded as one of the key enabling component to achieve three-dimensional (3D) integrated circuit (IC) functionality. In this paper, we present the investigation on TSV protrusion and stress at different annealing conditions tested by means of optical profiler and high efficiency micro-Raman microscopy. Finite element method is utilized to model and simulate the thermo-mechanical behavior of the TSV having a diameter of 20 μm and a depth of 120 μm under different annealing temperatures. The measured protrusion increases with annealing temperature below 400°C, and then decreases when being further annealed. The maximum measured silicon stress as a function of annealing temperature has shown similar trend to the protrusion. The pre-annealing has limited effect on protrusion, but is helpful to reduce the silicon stress.

TSV (through silicon via) is regarded as a key technology for 2.5D and 3D electronic packaging. And the manufacturing of the through silicon interposer is very challenge and costly. In the backside process of interposer, grinding is considered as the most promising technology to control wafer's surface roughness and surface defect. In this paper, according to the grinding process, a mathematical model is established. According to the model, MATLAB is used to simulate and predict the grinding marks and the distance between two adjacent grinding lines during the backside grinding process. The grinding marks of the half contact grinding model and full contact grinding model with different wheel rotation speed and wafer rotation speed are presented. And the relationship between two adjacent grinding lines and the ratio of wafer rotation speed and wheel rotation speed is predicted. The experiments are also carried out to verify the proposed model. The results of the experiments agree well with the simulation results.

In the paper, an equivalent modeling method is proposed to simplify thermal simulation model of 2.5D stacked dies modules. A TSV and its surrounding silicon substrate or a micro bump and its surrounding underfill will be equivalent to a single body of material. Through this method, we will not only be able to obtain thermal characteristics of each part of the stacked dies module, but also can greatly simplify the calculation amount of numerical simulation. According to this method, we obtained thermal distribution map of 2.5D/3D stacked dies module; in addition, to guide and optimize thermal management design, we analyzed the influence of several parameters on maximum junction temperature of 2.5D stacked dies as well, such as spacing among dies, thermal conductivity of TIM2 (Thermal Interface Material), ambient temperature, wind speed and so on. It was found that with the increase in spacing among dies, the maximum junction temperature of dies decreases and the maximum decreasing amplitude is 4.4°C. Secondly, impact on the maximum junction temperature of die, the ambient temperature of the cabinet is the most serious. Finally, the wind speed of the cabinet and the thermal conductivity of TIM2 (Thermal Interface Material) also have a great effect on the maximum junction temperature of die.

Thermal stress is induced by high temperature manufacturing processes, due to the mismatch of Coefficient of Thermal Expansion s (CTE) between silicon, dielectric material and copper. In this paper, thermal stress around Through-Silicon-Vias (TSVs) was discussed using 3D FEA transient method. Stress distributions near a TSV and TSVs array were investigated after dielectric liner deposition, barrier layer deposition and annealing process, respectively. Moreover, stress distribution around a via was impacted by the thickness of the dielectric liner, the via diameter, the via pitch and the cooling speed during annealing process. In order to verify the simulation results, TSV samples were fabricated through a series of processes. Si Raman shift profiles near a TSV was also measured and calculated. The simulation results coincided with the real measurement value in tolerable error range.

TSV was regarded as the core technology enabling 3D IC integration. For volume production, the requirement of low-cost TSV fabrication process was a big challenge. In order to find a fast filling method, new Cu plating solutions are desirable and some new filling method using solder, Cu cored solder ball were studied. A new TSV structure composed of intermetallic compounds (IMCs) was proposed in present paper and the manufacturing process was introduced. To form such a TSV structure, it needs to fill liquid solder into the vias and accelerate the inter-diffusion of solder and metal on the sidewall of the vias by annealing. The feasibility of the formation of IMC TSVs was studied using SnPb solder. The solder was filled into the vias in which partial annular Cu layer was plated. Successful voids free filling with thin protrusion of solder material on the top of the vias was achieved. Finite element analysis (FEA) of TSV filling with Cu, solder and Sn-based IMC were carried out and the results showed that the IMC filled TSVs can get comparable or even lower stress depending on the CTE of the IMCs. According to present results, it can be concluded that the IMC TSVs have the following merits: fast and low cost forming process, good high temperature stability and the lower stress.

Detecting through silicon via (TSV) associated defects non-destructively immediately after the fabrication process, or in failure analysis is of great interest and is a challenge. This paper reports on the inspections of 5 to 30 μm diameter TSVs by the state-of-the-art, commercially available X-ray systems, exemplifying a generally preferred method for non-invasively identifying metallization defects in vias as well as in joining structures. The principle of X-ray imaging for TSV measurement is discussed and illustrated, and three dimensional TSV structures are reconstructed by computed tomography (CT). Methods to achieve high-resolution TSV X-ray imaging are discussed.

The Filling of high aspect ratio through silicon vias (TSVs) using copper plating without any void or seam is one of the technical challenges for 3D integration. This paper presents numerical simulation and experimental verification of copper plating with different additives and a guideline for process optimization is proposed. Theoretical models are derived and a generic calculating approach is developed by employing a variable boundary method using commercial software. The simulation results can predict the behaviors of copper plating with different levels of additives for blind vias. The further experimental results verified the theoretical model and the simulation results. TSVs with diameter of 30μm and depth of 160μm on 8 inch wafers without void or seam have been achieved.

In this paper, interfacial failures (delamination and crack) of a MEMS device during humidity reliability testing are described. Three failure mechanisms are identified: thermal/mechanical stress due to the mismatch in the CTE (Coefficient of Thermal Expansion) of different materials. hygroscopic stress due to moisture absorption and swelling of polymer materials characterized by the CME (coefficient moisture expansion) and hygroscopic-thermal stress considering steam driven stress are analyzed. The observed regular failure pattern of the device suggests that the roles of thermal stresses and CME mismatch-induced hygrostress in interfacial failures of the device during reflow are minor, and that delamination and crack during reflow are primarily driven by evaporated steam. In order to solve the reliability problems, Physical size, process and material of the device are optimized. Simulation plays a key role in the study of the influence of the physical size of the device. Meanwhile, a new package structure with double seal rings is proposed, which greatly reduces the effect of steam-driven stress. Following the modifications suggested by the simulations, the MEMS device passed the temperature/humidity test.

With the miniaturization of electronic packages, fine pitch interconnect technology becomes increasingly important and new fabrication techniques have to be developed. For micro-bumps with diameter less than 50μm, undercutting can occur at the seed layer etching step and it will affect the bonding strength of micro-bumps. In this paper we explore a number of methods to reduce and avoid undercutting by selecting different etchants formulations and concentrations for the Ti adhesion layer and Cu seed layer. Through a series of experiments, we observed the following results. 50% solution of 1NH4OH (25%): 1H2O2 (30%) can be used as a Cu seed layer etchant. However at high concentrations the Cu pillar would be attacked. 2CH3COOH (50%): 1H2O2 can also be used to etch the Cu seed layer. And diluted 1HNO3 (50%): 1HF (40%) can be used to etch the Ti adhesion layer. Etching results are very satisfactory. By careful adjustment of etch recipe we have obtained Cu/Sn micro-bumps having a 30μm in diameter and 50μm in pitch with minimal undercutting.

Through silicon vias (TSVs) attract considerable amount of attention and activity in recent years as a main means to achieve three-dimensional (3D) integrated circuit (IC) functionality. However, the new technology poses new integration challenges as well as new testing and verification challenges. This paper presents the latest progress in TSV non-destructive testing by means of X-ray microscopy, a technique which is approved to be the method of choice for identifying metallization defects in vias. The principle of X-ray imaging system for TSV measurement is illustrated. By using commercially available X-ray microscopy tools, metallization defects in vias having a diameter of 30 μm and a depth of 160 μm can be visualized under optimized conditions.

In this paper several heat dissipation mechanisms are studied in an effort to improve heat dissipation of a high-power packaged chip in its environment. Specifically we examine a cavity-down structure consisting of a copper plate in thermal contact with the back side of the chip. In order to evaluate the thermal performance of the cavity-down approach, three structures are compared via simulation. Heat transport occurs by conduction, radiation and convection. The first depends on material properties, thickness and temperature gradient. The second is only effective if the temperature of the radiator is much higher than that of the absorber and the two are in close proximity. Convection is most effective at high mass flow and large differential temperatures. For the problem at hand we consider, several different thicknesses of the copper heat spreader to optimize conduction within the bounds of the package. In addition, forced air convection is optimized, within the package limitations. Optimum cooling conditions are obtained by parameterization of variables: air flow direction, fan position, and package placement.

This paper reports a novel anemometer configuration for airflow measurement. The flow over a sphere provides an ideal flow geometry. Four micro hot-film sensors are orthogonally mounted on the circumference of a sphere. The airflow speed distribution on the sphere as well as flow separation point will affect heat dissipation of the hot-film sensors, and result in variance of resistance of the sensors. By using the information from four positions, 2-D airflow speed and direction can be reconstructed. The micro hot-film sensor die was first designed and fabricated, and then packaged and assembled into a plastic sphere. The wind tunnel testing of the sensor prototype reveals good sensitivity and directivity, indicating it is feasible for environmental airflow measurement.

A new method for realization of 3D multilayer micro structures is presented in this paper. It consists of two major processes: silicon etching process and UV-LIGA process. In this way, some shape limitations of single technology can be overcome for new functions. By combining these processes, multilayer structures and complex graphics can be fabricated. To make good combination, the adhesive characteristics between the SU-8 photoresist and the surface of etched silicon substrate was studied. Two steps that can thoroughly remove bubbles in the etched silicon groove are also employed. To demonstrate this combination of micro fabrication process, some SU-8 microstructures are successfully fabricated in the etched silicon grooves. This method has applications in multi-layer microstructure fabrication.

We present a bilayer cantilever microelectromechanical systems probe card configuration aiming to achieve an optimization of the mechanical and electrical properties of the probes. This bilayer cantilever structure is analyzed by an analytical method, and then further validated by finite element analysis. A prototype probe card structure is designed for the parallel I/O pads layout with a pitch of 100 µm, and developed via combining Si micromachining and ultraviolet Lithographie, Galvanoformung, Abformung (lithography, electroplating, and molding) (UV-LIGA) technique. The measured spring constant of the cantilever is 0.6362 Nm-1, close to the theoretical prediction. The resistance from the probe tip to the end of the Cu conductive line is as low as 0.035 , indicating a very small electrical loss on the probe structure. In the radio frequency (rf) range of 0 to 40 MHz, the characteristic impedance is higher than 20 k, while the capacitance between two adjacent probes is around 0.13 pF. These measurement data indicate that the designed cantilever probe card structure has a good rf isolation property that makes it suitable for the testing of high-speed signal ICs.

For integrating thick microstructures with microfabricated circuitry on the same chip, a metal foundation method to consolidate adhesion of the electroplated microstructures to the substrate for successful removal of SU-8 mould is proposed. Along with multilevel interconnections microfabrication or other required metal deposition, the metal foundations are constructed and then tamped by interlevel dielectric. With metal foundations formed along with fabrication of interconnections and thin film electrodes, the electroplated Ni structures of an electrostatically levitated rotational microgyro, with thickness of 200 µm after lapping the whole wafer, are successfully released by removing the SU-8 mould using the fuming sulphuric acid oxidising method.