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This paper presents a new high speed gate driver circuit driven by In-Zn-O thin film transistors. Two methods are employed to improve the speed of this dirver: First, the input stage multiplex structure is adopted, one input stage drives three output stages; this could reduce the quantity of thin film transistors and also could achieve the narrow bezels in the AMOLED or AMLCD displays. Even the work frequency of the input stage becomes 1/3 of the output stage. When the speed of the circuit increass, there is enough time for input stage charging and discharging. So this kind of driver is suitable for high speed driving method. Second, three times the capacitance coupled effect generated in the gate driver can pull up the voltage level of the key nodes in the circuit, ensuring the signal integrity, While the first time the effect generated in the input stage is to reduce the charge time of the cascade signal and improve the speed of input stage. The second time that generated between input stage and output stage contrbutes to the integrity of cascade ouput signal and output control signal. A diode-connected thin film transistor applied to connect the output control signal and the gate of pull-up thin film transistors in output stage generates the three time capacitance coupled effects. Since the capacitance coupled effect can pull up the gate voltage of the pull-up thin film transistors during output period, the driving ability of the pull-up thin film transistors and the working speed could be promoted effectively. Simulation result shows that the capacitance coupled effect of each key node can pull up the voltage level considerably and the gate driver can normally work at the speed of 4 s. Finally, ten stage gate driver circuits have been fabricated successfully including ten input stages and thirty output stages. The test result shows that the proposed gate driver could work normally with a load of R=5 k and C=100 pF. Furthermore, the high speed test result shows that the output signal pulse width of the circuit is 2 s meeting the driving demands of the 4 k8 k display at the frame rate of 120 Hz. The power consumption of the gate dirver circuit is measured in different resolutions under the frame frequencies of 60 and 120 Hz respectively.

A new voltage-programmed driving scheme named the mixed parallel addressing scheme is presented for AMOLED displays, in which one compensation interval can be divided into the first compensation frame and the consequent N −1 post-compensation frames without periods of initialization and threshold voltage detection. The proposed driving scheme has the advantages of both high speed and low driving power due to the mixture of the pipeline technology and the threshold voltage one-time detection technology. Corresponding to the proposed driving scheme, we also propose a new voltage-programmed compensation pixel circuit, which consists of five TFTs and two capacitors (5T2C). In–Zn–O thin-film transistors (IZO TFTs) are used to build the proposed 5T2C pixel circuit. It is shown that the non-uniformity of the proposed pixel circuit is considerably reduced compared with that of the conventional 2T1C pixel circuit. The number of frames (N) preserved in the proposed driving scheme are measured and can be up to 35 with the variation of the OLED current remaining in an acceptable range. Moreover, the proposed voltage-programmed driving scheme can be more valuable for an AMOLED display with high resolution, and may also be applied to other compensation pixel circuits.