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Looking forward to the next generation of mobile streaming computing, the demanded energy efficiency of end-user terminals will become ever stringent. The Xetal-Pro processor, which is the latest member of the Xetal low-power single-instruction multiple data (SIMD) processor family from Philips, is presented in this paper. The predecessor of Xetal-Pro, known as Xetal-II, already ranks as one of the most computational-efficient [in terms of giga operations per second (GOPS)/Watt] processors available today, however, it cannot yet achieve the demanded energy efficiency (less than 1 pJ per operation). Unlike Xetal-II, Xetal-Pro supports ultrawide supply voltage (Vdd) scaling from the nominal supply to the subthreshold region. Although aggressive Vdd scaling causes severe throughput degradation, this can be partly compensated for by the massive parallelism in the Xetal family. Xetal-II includes a large on-chip frame memory (FM), which cannot be scaled well to an ultralow Vdd hence creating a big obstacle to increase energy efficiency. Therefore, we investigate both different FM realizations and memory organization alternatives. A hybrid memory system (HMS), which reduces the non-local memory traffic and enables further Vdd scaling, is proposed. For design space exploration of the right number of the scratchpad memory (SM) entries, the corresponding data locality analysis is provided, too. Moreover, some unique circuit implementation issues of Xetal-Pro such as the customized level-shifter are also discussed. Compared to Xetal-II operating at the nominal voltage, Xetal-Pro provides up to two times energy efficiency improvement even without Vdd scaling (essentially a consequence of data localization in the SM) when delivering the same amount of ultrahigh throughput. With Vdd scaling into the sub/near threshold region, Xetal-Pro could gain more than ten times energy reduction while still delivering a high throughput of 0.69 GOPS (c ounting multiply and add operations only). The new insight of Xetal-Pro sheds light on the direction of future ultralow-energy SIMD processors.

A processor architecture combining high-performance and low-power is presented. A prototype chip, Xetal-II, has been realized in 90 nm CMOS technology based on the proposed architecture. Recent experimental results show a compute performance of up to 140 GOPS at 785 mW when operating at 110 MHz. The main architectural feature that allows high computational efficiency is the massively-parallel single-instruction multiple-data (MP-SIMD) compute paradigm. Due to the high data-level parallelism, applications like video scene analysis can efficiently exploit the proposed architecture. The chip has an internal 16-bit datapath and 10 Mbit of on-chip video memory facilitating energy efficient implementation of video processing kernels.

Xetal-II is a single-instruction multiple-data (SIMD) processor with 320 processing elements. It delivers a peak performance of 107 GOPS on 16-bit data while dissipating 600 mW. A 10 Mbit on-chip memory is provided which can store up to four VGA frames, allowing efficient implementation of frame-iterative algorithms. A massively parallel interconnect provides an internal bandwidth of more than 1.3 Tbit/s to sustain the peak performance. The IC is realized in 90 nm CMOS and takes up 74 mm2.

This paper presents Xetal-Pro SIMD processor, which is based on Xetal-II, one of the most computational-efficient (in terms of GOPS/Watt) processors available today. Xetal-Pro supports ultra wide V DD scaling from nominal supply to the sub-threshold region. Although aggressive V DD scaling causes severe throughput degradation, this can be compensated by the nature of massive parallelism in the Xetal family. The predecessor of Xetal-Pro, Xetal-II, includes a large on-chip frame memory (FM), which cannot operate reliably at ultra low voltage. Therefore we investigate both different FM realizations and memory organization alternatives. We propose a hybrid memory architecture which reduces the non-local memory traffic and enables further V DD scaling. Compared to Xetal-II operating at nominal voltage, we could gain more than 10× energy reduction while still delivering a sufficiently high throughput of 0.69 GOPS (counting multiply and add operations only). This work gives a new insight to the design of ultra-low energy SIMD processors, which are suitable for portable streaming applications.

There is a rapidly growing demand for cameras containing built-in intelligence for various purposes such as surveillance and identification. Face recognition is an important application for these cameras. Previous research has shown that faces can be well represented by parabola segments using an algorithm which fits parabola segments to edge pixels. Faces are then recognized using a technique which matches parabola segments based on distance and intensity. Considerable computational resources are required for the extraction of the parabola primitives, due to the need for Canny edge detection. This algorithm is well-suited for the new generation of massively parallel SmartCams though, if it is represented in a highly parallelized, low complexity representation adapted to the characteristics of these SmartCam architectures. This paper proposes such an implementation of the Canny edge detection algorithm for the Single Instruction Multiple Data (SIMD) Xetal IC3D processor, resulting in a real-time performance using a smart camera not bigger than a typical surveillance camera.

Optical Character Recognition (OCR) techniques are widely used in data/text entry, process automation. Decades of research efforts have made the accurate recognition of typewritten text largely accepted as a solved problem. Driven by practical usage demands, the low complexity and high performance implementation techniques of OCR systems are studied. Recent research shows that it may not be possible even for a simple OCR to run on a portable device without a specialized digital signal processor. In this paper, we present a highly data-parallelized implementation of OCR for typewritten text onto the linear processor array of the Xetal chip. Besides the preprocessing stage, the most computation intensive part of OCR recognizing individual characters is highly parallelized onto the Single Instruction Multiple Data (SIMD) engine of the Xetal chip, which can process a VGA-resolution text frame within one tenth of a second. In addition, different parallelization schemes are explored to make trade-off between the degree of parallelism and the costs of preprocessing to reorganize data to feed the SIMD engine and post-processing to assemble and collect results. The exploration of parallelized OCR application brings additional performance gain when mapped onto the linear processor array of the Xetal chip.

Xetal-II is a SIMD processor with 320 processing elements delivering a peak performance of 107 GOPS on 16b data while dissipating 600mW. A 10Mb on-chip memory can store up to 4 VGA frames allowing efficient implementation of frame-iterative algorithms. A massively parallel interconnect provides an internal bandwidth of more than 1.3Tb/s to sustain the peak-performance. The 74mm2 IC is fabricated in 90nm CMOS.

The XETAL chip by Philips Electronics is a low-cost hardware-solution for image processing on pixel level. The architecture of XETAL focuses on a low-energy environment and it is therefore highly suited for integration into mobile vision and intelligent cameras. While hardware support for 2D-vision has reached the level of affordable state-of-the-art technology by thorough research, also real-time 3D-vision by stereo, based on the support by a low-cost and low-energy hardware, appears to be able to reach this level soon.

Single-Instruction Multiple-Data (SIMD) processing is valuable in numerous compute intensive application areas, especially in pixel processing on programmable processors. With SIMD, the nice thing is that the actual hardware can be scaled to the performance and the power consumption demands of the application domain, while the software suite remains equal. In this paper, we discuss the effect of scaling on power consumption, cost and performance which is related to the characteristics of applications ranging from mobile to medical video processing. Our analysis is based on experience obtained with the Philips Xetal SIMD processor [1,2].

Xetal is a digital signal processor to be combined with a 30 frames per second VGA-format CMOS or CCD image sensor or any other source of digital video data. The processor is fully programmable and therefore able to run a variety of algorithms ranging from image communication to machine vision. Xetal comprises a parallel processor array and a special purpose controller to achieve high computational performances (up to 5 GOPS) with a very modest power consumption. This can go down to 30 mW for simple applications such as a digital camera for video conferencing. The Xetal chip has been realized in a 0.18 /spl mu/m CMOS process and takes up an area of 25 mm/sup 2/.

A transpose switch matrix memory (TSMM) is proposed to enable a highly parallel single-chip CMOS sensor/image processor, Xetal, developed at Philips to perform JPEG compression at video rate (30 frames per second, fps) at an image dimension of 640/spl times/480 pixels. The integrated solution consists of 320 processing elements and 80 TSMMs, operates at 16 MHz clock rate and 3.3 V supply voltage, and is designed for fabrication at 0.25 micron technology. The processing system can sustain a maximum throughput of 5.12 billion operations per second consuming an estimated 120 mW providing a processing power efficiency of 7 BOPS/Watt. The Xetal architecture is capable of performing pixel level image processing such as fixed pattern noise (FPN) correction, defective pixel concealment, Bayer pattern filtering, RGB-YUV conversion, auto white balancing, and auto exposure control. The TSMM expands support to block level operations including chrominance subsampling, separable 8/spl times/8 recursive DCT, and ZZ scan required for JPEG.