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An oxide fin-based AND flash memory synaptic device is proposed and fabricated using a spacer patterning technology for a hardware-based binary neural network (BNN). A fin-like curved channel structure provides local electric field enhancement, which improves programming efficiency compared to planar-type flash synaptic devices. The fin-based AND flash cell exhibits a high on/off current ratio (>105) with sub-pA off current, and a low programming voltage ( 103) for BNNs. Furthermore, a hardware-based BNN using novel two cell-based synaptic devices arranged in AND array architecture is proposed to implement parallel XNOR operation and bit-counting. Proposed BNN using the synapse model with measured dynamic range and retention property shows only

In this letter, we propose a double-gated ferroelectric-gate field-effect-transistor (DG-FeFET) for processing-in-memory (PIM) operations in a single device for the first time. The proposed device is highly compatible with a conventional fin field-effect-transistor (FinFET) process and thus the scalable Fin FeFET with the completely sympatric double gates can be fabricated by adding only one gate metal recess process. After the rigorous calibrations of the ferroelectric and device technology computer aided design (TCAD) models by utilizing the fabricated ferroelectric capacitor and planar FeFET, it is demonstrated that the 16-Boolean logic operations including XNOR, NAND and AND can be stably implemented in a single DG-FeFET through energy-efficient two step operation scheme.

Inverters or logic primitives that have complement attributes are essential to building a logical complement system. NAND and NOR operations which have complement attributes are of high interest for complementary metal-oxide-semiconductor (CMOS) technology, as they can be easily implemented in transistors. Different from the logic models used in standard CMOS, several nano-emerging technologies, such as quantum-dot cellular automata (QCA) and spin torque majority gates, are in favor of realizing a majority voter function but imposing difficulties in implementing inversions. Previous studies pay lots of effort in optimizing the number of inverters in logic representations, whereas the mapping using primitives with complement attributes is not a major concern. In this paper, we establish a technology mapping method from logic representations to nanotechnology primitives by considering NAND-NOR-Inverter (NNI) and exclusive-NOR (XNOR) operations. We adopt XOR-Majority Graph (XMG) as a logic representation. The proposed mapping method is evaluated using the QCA technology. Experimental results over EPFL benchmark suites show we achieve 11.77% and 30.13% reductions in the area and the number of inverters, respectively.

We have investigated the spin-Hall effect (SHE)-assisted spin transfer torque (STT) switching mechanism in a three-terminal MTJ device developed using p-MTJ (perpendicular magnetic tunnel junction) and heavy metal materials of high atomic number, which possesses large spin–orbit interaction. Using p-MTJ schematic and complementary-metal-oxide-semiconductor (CMOS) logic, we have designed three basic hybrid logic-in-memory structure-based logic gates NOR/OR, NAND/AND, and XNOR /XOR. Then the performances of these hybrid gates are evaluated and the results are compared with the conventional CMOS-based gates in terms of power, delay, power delay product, and device count. From the analysis, it is concluded that SHE-assisted STT MTJ/CMOS logic gates are nonvolatile, consume less power, and occupy a smaller die area as compared to conventional CMOS only logic gates.

Electronic circuits operating in the radiation intensive environment like space, are subject to a barrage of cosmic particles like neutrons, protons, and heavy ions which can cause voltage glitches in various nodes of circuits causing single event upsets (SEUs) that can cause catastrophic failures. SEU tolerant circuits are required to improve reliability of electronic circuits in radiation prone environment. This paper proposes an improved split-output SEU tolerant logic gate whose outputs swing rail-to-rail thereby improving the noise-margin. The proposed design achieves equal delays for both the outputs thereby facilitating easier characterization of delays for creation of Synopsys Liberty timing libraries for seamless integration with the existing place-and-route tools. A standard-cell library comprising of inverter, two-input NAND, NOR, XOR, and XNOR, tri-state inverter, and D-flip-flops with set, reset, and both set-reset, were designed for various drive strengths in TSMC-28 nm and UMC-180-nm CMOS technology. The proposed logic gates have been simulated up to $$120\ MeV$$ - $$cm^2/mg$$ of Linear Energy Transfer (LET) and have been found not to cause bit flips in the subsequent stage.

This article (Colonnade) presents a fully digital bit-serial compute-in-memory (CIM) macro. The digital CIM macro is designed for processing neural networks with reconfigurable 1–16 bit input and weight precisions based on bit-serial computing architecture and a novel all-digital bitcell structure. A column of bitcells forms a column MAC and used for computing a multiply-and-accumulate (MAC) operation. The column MACs placed in a row work as a single neuron and computes a dot-product, which is an essential building block of neural network accelerators. Several key features differentiate the proposed Colonnade architecture from the existing analog and digital implementations. First, its full-digital circuit implementation is free from process variation, noise susceptibility, and data-conversion overhead that are prevalent in prior analog CIM macros. A bitwise MAC operation in a bitcell is performed in the digital domain using a custom-designed XNOR gate and a full-adder. Second, the proposed CIM macro is fully reconfigurable in both weight and input precision from 1 to 16 bit. So far, most of the analog macros were used for processing quantized neural networks with very low input/weight precisions, mainly due to a memory density issue. Recent digital accelerators have implemented reconfigurable precisions, but they are inferior in energy efficiency due to significant off-chip memory access. We present a regular digital bitcell array that is readily reconfigured to a 1–16 bit weight-stationary bit-serial CIM macro. The macro computes parallel dot-product operations between the weights stored in memory and inputs that are serialized from LSB to MSB. Finally, the bit-serial computing scheme significantly reduces the area overhead while sacrificing latency due to bit-by-bit operation cycles. Based on the benefits of digital CIM, reconfigurability, and bit-serial computing architecture, the Colonnade can achieve both high performance and energy efficiency (i.e., both benefits of prior analog and digital accelerators) for processing neural networks. A test-chip with $128 \times 128$ SRAM-based bitcells for digital bit-serial computing is implemented using 65-nm technology and tested with 1–16 bit weight/input precisions. The measured energy efficiency is 117.3 TOPS/W at 1 bit and 2.06 TOPS/W at 16 bit.

In this project, novel circuits for FULL ADDER are proposed using new XOR or XNOR gates. The conventional design of XOR or XNOR gates shows that the not gate in the schematic has drawbacks. So by investigating advanced XOR or XNOR gates we proposed the schematic design. The proposed schematics are optimized in terms of speed, delay, power and power delay product. We developed six novel hybrid full adder schematics based on exploring new XOR or XNOR gates. Each designed schematics have their specifications of energy consumption, delay, power delay product. To simulate the performance of the proposed designs, we use mentor graphics, tanner tool. The simulation yields a 45-nm CMOS innovation model that focuses on the proposed plans having best speed and power other than the plan of any full adder. The proposed Full Adders has 2-28% increment in consumption of energy and power delay product compared to other design schematics. The proposed hybrid full adders are investigated with voltage 1.8V, speed ,size of transistors, area, power consumption and delay.

Conjunctive normal forms (CNF) of structured satisfiability problems contain logic gate patterns. So Boolean circuits (BC) by and large can be obtained from them and thus structural information that is lost in the CNF can be recovered. However, it is not known which logic gates are useful for local search on BCs or which logic gates in particular help local search the most and why. In this article, we empirically show that exploitation of xor, xnor, eq, and not gates is a key factor behind the performance of local search algorithms using single variable flips when adapted to logic gate constraints. Moreover, controlled experiments and investigations into the variables selected for flipping further elucidates these findings. To achieve these conclusions, we have adapted the AdaptNovelty+ and CCANr algorithms to cope with logic gate-based constraint models. These are two prominent families of local search algorithms for satisfiability. We performed our experiments using a large set of benchmark instances from SATLib, SAT2014, and SAT2020. We have also presented techniques to eliminate cycles among logic gates that are detected from CNF and to propagate equivalence of variables statically through the logic gate dependency relationships.

A single biological neuron can efficiently perform Boolean operations. Artificial neuromorphic systems, on the other hand, typically require several devices to complete a single operation. Here, we show that neuristors that exploit the intrinsic polarity of two-dimensional materials can perform logic operations in a single device. XNOR gates can be made using ambipolar tungsten diselenide (WSe2), NOR gates using p-type black phosphorus, and OR and AND gates using n-type molybdenum disulfide (MoS2) of different thicknesses. To illustrate the potential of the neuristors, we fabricate logic half-adder and parity-checker circuits using a WSe2 neuristor and a MoS2 neuristor in a two-transistor two-resistor configuration, offering an area saving of 78% compared to circuits based on MoS2 gates in a traditional design. We also propose a binary neural network that is based on a three-dimensional XNOR array, which simulations show should offer an energy efficiency of 622.35 tera-operations per second per watt and a power consumption of 7.31 mW. By using two-dimensional materials with different polarities, single neuristors can act as XNOR, NOR, OR and AND logic gates.

This work reports a new circuit of a three-bit digital controlled ring oscillator (DCRO) in TSMC 180 nm CMOS technology with low-power consumption. The reported DCRO circuit is designed with the digitally controlled delay element employing three transistors (3 T) XNOR gate and inversion MOS varactor (IMOS). Delay cell consists of an XNOR-based inverter, a switching network designed using PMOS transistors, and a capacitive load element designed using MOS varactors. Driving current into the delay stages is controlled by the switching network, and output frequency tuning is achieved with this switching network. Further, with the variation of digitally controlled MOS varactors capacitance in the load element, output frequency variation in the DCRO is obtained. Using the discrete combination of digital bits in the switching network, DCRO oscillates in the frequency span of 0.890 GHz–0.724 GHz. Load capacitance alters with the change in digital control bits of MOS varactors, and DCRO oscillates from 0.890 GHz to 0.916 GHz. Further, applying the change in supply voltage from 1 to 2 V, a frequency tuning range of 0.682 GHz––1.222 GHz is achieved with power variation from 2.760 mW to 9.786 mW. Proposed DCRO exhibits a phase noise of − 93.905@1 MHz offset from central oscillation frequency. DCRO shows a figure of merit (FoM) of 158.84 dBc/Hz at 0.916 GHz output frequency with consumed power of 0.269 mW at 1.8 V power supply voltage.

The real time systems are designed by using analog and digital sub systems with control logic. In the design of digital sub systems the logic gates are the major building blocks. The Neural Networks found many applications in the areas of pattern recognition, prediction, artificial intelligence and other applications. Most of the Neural Network designs are realized by using software domain and hardware domains. This paper presents the hardware realization of logic gates using Neural Network. The logic gates like NAND, AND, NOR, OR, NOT, BUFFER are realized by using single layer neural network. The XNOR and XOR logic gates are realized by using structural representation of neural network based universal NAND gates. All the logic gates are realized by using Verilog HDL with Xilinx Vivado Design suite targeting for Xilinx Zynq-7000 SoC Evaluation Board. The Neural Network based logic gates are simulated for different test cases. Index Terms: Neural Network, Logic Gate, Zynq-7000 SoC, Verilog HDL, Xilinx Vivado EDA tool.

To improve the performance of all-digital synthesizable comparators for the stochastic circuit, we present a three-stage rail-to-rail fully synthesizable dynamic voltage comparator. Compared with the state-of-the-art designs, the proposed comparator uses XOR, XNOR, NAND, and NOR logic gates to further improve the comparator’s common-mode input range, offset, speed and power-delay product (PDP). The comparator is implemented on CMOS 45 nm technology, operating with a supply voltage of 250 mV–1.0 V. The comparator has reduced the delay by 0.70 to $$0.82\times $$ , increased the standard deviation of offset by 1.28 to $$1.65\times $$ and reduced the PDP down to $$0.67\times $$ compared to NAND & NOR-based comparator. Hence, these improvements help to increase the performance of the stochastic Flash ADC, and improve the reliability of the stochastic PUF circuit.

The conventional SOA suffers from the problem of the finite gain recovery time that limits its application at higher data rates. Therefore, in the present paper, we employ a carrier reservoir semiconductor optical amplifier (CR-SOA) as an alternative device to realize the all-optical NAND and XNOR logic gates for 120 Gb/s return-to-zero data, for the first time to our knowledge. For this goal, a pair of symmetrical CR-SOAs are incorporated in properly driven and combined Mach–Zehnder interferometers (MZIs), which constitute an appealing technological choice for all-optical switching purposes. The CR-SOA performance is compared against that of the conventional SOA for both considered logic gates. This is done by evaluating the quality factor and associated bit error rate, as well as the quality of the logic outcome. The results reveal the superiority of the CR-SOAs-based MZIs for realizing the logic NAND and XNOR gates at 120 Gb/s by achieving acceptable performance, as opposed to the conventional SOAs-based MZIs for which this is not possible.

DNA logic gated operations empower the highly efficient analysis of multiplex nucleic acid inputs, which have attracted extensive attention. However, the integration of DNA logic gates with abundant computational functions and signal amplification for biomedical diagnosis is far from being fully achieved. Herein, we develop a bipedal DNA walker based amplified electrochemical method for miRNA detection, which is then used as the basic unit for the construction of various logic circuits, enabling the analysis of multiplex miRNAs. In the bipedal walking process, target triggered strand displacement polymerization is able to produce a large number of strands for the fabrication of three-way junction-structured bipedal walkers. The following catalytic hairpin assembly ensures the walking event and the immobilization of signal probes for output. Ultrahigh sensitivity is realized due to the integration of dual signal amplification. In addition, under logic function controls by input triggered cascade strand displacement reactions, NOT, AND, OR, NAND, NOR, XOR, and XNOR logic gates are successfully established. The as-developed DNA logic system can also be extended to multi-input modes, which holds great promise in the fields of DNA computing, multiplex analysis, and clinical diagnosis., Cascade strand displacement reactions are developed for the construction of a series of miRNA responsive logic gates with bipedal walking for electrochemical signal outputs.

Recent studies on neural network quantization have demonstrated a beneficial compromise between accuracy, computation rate, and architecture size. Implementing a 3D Vertical RRAM (VRRAM) array accompanied by device scaling may further improve such networks’ density and energy consumption. Individual device design, optimized interconnects, and careful material selection are key factors determining the overall computation performance. In this work, the impact of replacing conventional devices with microfabricated, graphene-based VRRAM is investigated for circuit and algorithmic levels. By exploiting a sub-nm thin 2D material, the VRRAM array demonstrates an improved read/write margins and read inaccuracy level for the weighted-sum procedure. Moreover, energy consumption is significantly reduced in array programming operations. Finally, an XNOR logic-inspired architecture designed to integrate 1-bit ternary precision synaptic weights into graphene-based VRRAM is introduced. Simulations on VRRAM with metal and graphene word-planes demonstrate 83.5 and 94.1% recognition accuracy, respectively, denoting the importance of material innovation in neuromorphic computing.

The aspire of the manuscript be near apply a 14T Full adder unit, so as to make use of little power by means of XOR and XNOR gate . The 4-bit binary adder is constructed in ripple carry adder arrangement. It has been urbanized for little power utilization in falling the no. of transistor. The power utilization be able to abridged by 49% with planned FA difference ate through regular FA. Every one replication outcome contain be approved elsewhere by with 32 nm CMOS technology. The replication outcome of 1-bit adder planned FA shows so as to the planned FA have little power utilization. The hardware accomplishment of 14T FA be agreed with Deep Sub micron Technology

Ultrafast current-driven domain wall (DW) motions have been realized in ferrimagnetic (FiM) nanowires. However, the FiM dynamics can be significantly affected by the Joule-heating. In this work, we propose a highly efficient XNOR logic gate by properly leveraging the thermal effect on the FiM DW motions. Its functionality and advantageous performance have been confirmed by the micromagnetic simulations. Moreover, majority logic and full adder functions can also be reconfigured based on the proposed scheme. Lastly, a fully FiM DW based binary neural network (BNN) is built, which provides low energy consumption, short delay and excellent accuracy.

By replacing multiplication with XNOR operation, Binarized Neural Networks (BNN) are hardware-friendly and extremely suitable for FPGA acceleration. Previous researches highlighted the potential exploitation of BNNs performance. However, most of the present researches targeted at minimizing chip areas. They achieved excellent energy and resource efficiency in small FPGA while the results in larger FPGA were unsatisfying. Thus, we proposed a scalable fully pipelined BNN architecture, which targeted on maximizing throughput and keeping energy and resource efficiency in large FPGA. By exploiting multi-levels parallelism and balancing pipeline stages, it achieved excellent performance. Moreover, we shared on-chip memory and balanced the computation resources to further utilizing the resource. Then a methodology is proposed that explores design space for the optimal configuration. This work is evaluated based on Xilinx UltraScale XCKU115. The results show that the proposed architecture achieves 2.24×–11.24× performance and 2.43×–11.79× resource efficiency improvement compared with other BNN accelerators.

Biomolecular modeling and its associated analytical software simulation tools have a significant role in the rapid progress of bio-inspired semiconductor technologies. This paper presents the implementation of logic gates using molecular modeling of a cytosine-based single-walled nanotube. Density functional theory in and the nonequilibrium Green’s function-based first-principles approach are used to perform the quantum mechanical calculations for the electronic transmission within the nanotube. The gated cytosine single-walled nanotube shows high current-voltage response during room-temperature operation where the electrode voltage is kept at ± 0.02 V. This is a first attempt towards the circuit-level modeling of logic gates using a cytosine nanotube. The quantum transport phenomenon of this analytical model is investigated using an atomistic software simulation technique. The basic logic gates and XNOR gate are implemented with the study of the current-voltage characteristics. The maximum current observed during the simulation process is 52.6 μA. Moreover, the local device density at different energy levels proves the candidature of cytosine nanotubes as logic gates. The transmission spectrum analysis also confirms the high channel conductivity at the central scattering region of the nanotube.

Optical logic gates are key elements in all-optical circuits and computing. However, the footprints of current optical logic gates are still on micrometer scale. There remains challenging for further miniaturization of the logic gates to nanometer scale. In this paper, a simple scheme for realizing ultra-compact universal linear-optical logic gates is proposed. All common logic gates (AND, OR, NOT, NAND, NOR, XOR, and XNOR) encoded via binary phase shift keying are achieved by using single rectangle plasmonic slot nanoantenna with a footprint of 200 nm by 50 nm, which considerably shrinks the dimensions of the device.

The leakage power, a.k.a. static power, increases in deep-submicron technologies due to short-channel effects. This article proposes a novel input-controlled leakage restrainer transistor (ICLRT)-based technique to reduce leakage power as well as the short-circuit power. The main idea is to place a PMOS and an NMOS ICLRT on top of the pull-up network (PUN) and at the bottom of the pull-down network (PDN), respectively, on all paths from either the supply voltage or the ground to the output. The ICLRTs are deliberately used as a stack structure while being controlled by the input signals to lead the output to stronger low and high logic levels. In fact, the proposed technique reduces the leakage and short-circuit currents and, consequently, powers by increasing the threshold voltage and decreasing the gate-source voltage of the main transistors. Using the proposed technique, logical NOT, NAND, NOR, XOR, and XNOR static gates are designed and evaluated by SPICE simulations in 22-nm BSIM4 (level-54 parameters) CMOS technology. Simulation results with 0.9-V power supply voltage show that power–delay product (PDP) is reduced by 27.66%, 16.7%, and 21.58% for NOT, NOR, and XOR with respect to its best counterpart and by 32.62%, 47%, 49.23%, and 38.77% for NOT, NAND, NOR, and XOR with respect to the conventional static CMOS structures. Furthermore, Monte Carlo analysis is also performed to ensure the stability and robustness of the circuit’s performance in the presence of the process, voltage, and temperature (PVT) variations.

Molecular logic computation has drawn extensive attention in the fields of bioanalysis, intelligent diagnostics of diseases and other nanotechnology areas. DNA-templated Au nanoclusters (DNA-AuNCs) possess some excellent features, including high luminescence, good photo-stability and easy preparation. Herein, taking these advantages of DNA-AuNCs, we have designed and constructed a universal platform of label-free and enzyme-free multiple molecular logic gates, including NOR, XNOR, IMPLY, OR, AND, and INHIBIT. The experimental results have demonstrated the feasibility of these logic gates operations using Hg2+, Cu2+, biothiols, melamine and pyrophosphate (PPi) as inputs. Thus, the universal platform can be utilized for the determination of biothiols, melamine and pyrophosphate (PPi) via logic outputs. The strategy exhibited low cost, easy operation and versatile design, and can offer a promising platform for the development of functional logic systems.

Artificial intelligence has been demonstrated for numerous applications including image recognition and processing, internet-of-things (IoT), and speech recognition. Recent neural network (NN) architectures escalating to perform these functionalities require deep-learning and deep NN (DNN) implementation. However, the present algorithm and circuit of DNN suffer from area and energy-efficiency. The usage of an energy-efficient and cost-effective binary NN (BNN) can mitigate the performance bottleneck. The basic component of BNN (the XNOR and accumulate module) is capable of replacing the conventional multiply-and-accumulate (MAC) operation. Among various emerging nonvolatile memories (NVMs), spintronics-based devices are attracting attention for the implementation of the aforementioned architectures. Multilevel voltage-controlled spin-orbit torque -based magnetic memory (MV-SOTM) spin device as synapse and voltage-controlled SOTM (V-SOTM) device as spin-neuron are capable of producing an all-spin NN. This article presents advanced XNOR operation using a computing-in-memory (CiM) mechanism wherein both V-SOTM and MV-SOTM (using series and parallel configuration) based synapses are compared. The MV-SOTM design dissipates 35.51% lesser energy as compared to the 1-bit V-SOTM. Further, the 8-bit synaptic crossbar array is implemented using both the devices with two output spin-neurons. These series and parallel MV-SOTM-based synaptic arrays consume 42.22% and 45.12% lesser power, respectively, as compared to 1-bit V-SOTM based synaptic array. Furthermore, the all-spin BNN design demonstrates a handwritten digit recognition application.

Quantum-dot Cellular Automata (QCA) has emerged as one of the alternative technologies for current CMOS technology. It has the advantage of computing at a faster speed, consuming lower power, and work at Nano- Scale. Besides these advantages, QCA logic is limited to its primitive gates, majority voter and inverter only, results in limitation of cost-efficient logic circuit realization. Numerous designs have been proposed to realize various intricate logic gates in QCA at the penalty of non-uniform clocking and improper layout. This paper proposes a Composite Gate (CG) in QCA, which realizes all the essential digital logic gates such as AND, NAND, Inverter, OR, NOR, and exclusive gates like XOR and XNOR. Reportedly, the proposed design is the first of its kind to generate all basic logic in a single unit. The most striking feature of this work is the augmentation of the underlying clocking circuit with the logic block, making it a more realistic circuit. The Reliable, Efficient, and Scalable (RES) underlying regular clocking scheme is utilized to enhance the proposed design?s scalability and efficiency. The relevance of the proposed design is best cited with coplanar implementation of 2-input symmetric functions, achieving 33% gain in gate count and without any garbage output. The evaluation and analysis of dissipated energy for both the design have been carried out. The end product is verified using the QCADesigner2.0.3 simulator, and QCAPro is employed for the study of power dissipation.

Organic entities like suitably functionalized naphthalene diimide (NDI) exhibited logical behaviours in response to various external stimuli and can be used to develop digital logic operations. The present findings include utilization of two congeners of NDI i.e., N1 and N2 for the successive turning ON/OFF of fluorescence with inclusion of acid and base. The recognition of the switching phenomenon of the probes N1 and N2 are applied to construct fundamental digital logic gates such as NOT, YES, IMPLICATION, INHIBIT, etc. The inputs to each of the logic gates are defined by the presence or absence of acid and base. Accordingly, the outputs generated from the gates are in the form of fluorescence ON or OFF status denoted by “1” and “0” respectively. Likewise, we have adopted Boolean algebra and its associated De-Morgan's theorem to build the combined logic gates such as XOR and XNOR gates. The proposed logic gates are validated by the optical behaviour of the congeners N1 and N2 in response to acid as well as base and the experimental results are confirmed by the theoretical predictions. The proposed work can have potential applications in next-generation logic based analytical applications.

Recently, building an efficient and robust model for object detection has attracted the attention of the vision community. Although binary networks have a fast inference speed, they cannot be used directly on mobile devices such as unmanned aerial vehicles (UAVs) because of their low detection accuracy. Different from improving the detection accuracy of a binary network by adjusting the network structure or adjusting the update gradient, we propose an improved binary neural network based on the block scaling factor XNOR (BSF-XNOR) convolutional layer. In addition, we propose a two-level densely connected network structure, which further enhances the network layer’s feature representation capabilities. Experiments using the TensorFlow framework prove the effectiveness of our algorithm in improving accuracy. Compared with the original standard XNOR network, the mean average precision (mAP) detected by our algorithm on the PASCAL VOC dataset was improved. The experimental results on the VisDrone2019 UAV dataset confirm that our method achieves a better balance between speed and accuracy than previous methods. Our algorithm aims to guide and deploy high-precision binary networks on the embedded device and solves the problem of low-precision binary networks.

We have monolithically integrated resistance random access memory (RRAM) array with oxide semiconductor channel access transistor in 3-D stack, achieved uniform memory characteristics of 1T1R cells at each layer, and demonstrated basic functionality of XNOR operation as in-memory computing for binary neural network (BNN) artificial intelligence (AI) applications. The integrated TiN/Ti/HfO2/Ti stack RRAM shows high on/off ratio with stable retention and endurance properties. The indium gallium zinc oxide (IGZO) channel field-effect transistor (FET) works as an access transistor, which realized the low-temperature process, high mobility, and high drive current for RRAM. With the peripheral circuit, we demonstrate the XNOR operation using a pair of 1T1R cells. The impact of RRAM bit error rate on neural network is also investigated, which indicates the property of error-resilience in BNN. The 3-D neural network built by this architecture has high potential to enable area-efficient, low-power, and low-latency computing.

Quantum dot cellular automata (QCA) is considered one of the most promising technologies to replace the current CMOS technology. Compared with the traditional transistor technology, the computation relies on a new paradigm based on the interaction between nearby QCA cells. It has significant advantages, such as operating frequency (THz), high device density, and low power consumption. In this brief, a novel XOR/XNOR-function logic gate with two inputs, two enable inputs and one output is proposed and designed in Quantum-dot Cellular Automata (QCA) nanotechnology. In order to demonstrate the functionality and capabilities of the proposed QCA-based XOR/XNOR architecture, performance is evaluated and analyzed. The proposed XOR/XNOR logic gate has a superb performance in terms of area, complexity, power consumption and cost function in comparison to some existing QCA-based XOR architectures. Moreover, some efficient circuits based on the proposed XOR/XNOR gate are designed in QCA.

Tunnel field-effect transistors (TFETs) are being examined as a possible replacement of MOSFETs for digital applications. However, TFETs have small ON-state current and, typically, exhibit reduced speed compared with conventional MOSFETs. Nevertheless, TFETs have some distinct characteristics that can be exploited for digital applications. In this article, using simulations, we show that a single device, in which two terminals are biased independently, can realize all primary two-input Boolean functions, such as AND, OR, NAND, NOR, XOR, and XNOR. By modifying the architecture of double-gate TFET (DGTFET) slightly and appropriately choosing device parameters, the Boolean functions AND, OR, NAND, NOR, and XNOR can be implemented. In addition, we propose a twin double-gate (TDG) TFET architecture, which can implement the inhibition functions $A'B$ and $AB'$ . By suitably combining the inhibition functions, an XOR functionality can be obtained in a single device. These implementations demonstrate that the unique characteristics of TFET, such as ambipolar conduction and dependence of tunneling on the gate–source/drain overlaps, can be exploited to realize logic functions compactly.

In recent years we have seen a growing number of edge devices adopted by consumers, in their homes (e.g., smart cameras and doorbells), in their cars (e.g., driver assisted systems), and even on their persons (e.g., smart watches and rings). Similar growth is reported in industries including aerospace, agriculture, healthcare, transport, and manufacturing. At the same time that devices are getting smaller, Deep Neural Networks (DNN) that power most forms of artificial intelligence are getting larger, requiring more compute power, memory, and bandwidth. This creates a growing disconnect between advances in artificial intelligence and the ability to develop smart devices at the edge. In this paper, we present a novel approach to running state-of-the-art AI algorithms at the edge. We propose two efficient approximations to standard convolutional neural networks: Binary-Weight-Networks (BWN) and XNOR-Networks. In BWN, the filters are approximated with binary values resulting in 32x memory saving. In XNOR-Networks, both the filters and the input to convolutional layers are binary. XNOR-Networks approximate convolutions using primarily binary operations. This results in 58x faster convolutional operations (in terms of number of the high precision operations) and 32x memory savings. XNOR-Nets offer the possibility of running state-of-the-art networks on CPUs (rather than GPUs) in real-time. Our binary networks are simple, accurate, efficient, and work on challenging visual tasks. We evaluate our approach on the ImageNet classification task. The classification accuracy with a BWN version of AlexNet is the same as the full-precision AlexNet. Our code is available at: urlhttp://allenai.org/plato/xnornet.

In this communication, a new semiconductor optical amplifier (SOA)-based module for multi-valued logic units using the cross-polarization modulation effect is proposed and analyzed. The design is simple and compact, consisting of only three SOAs and a few passive optical elements. SOAs have very low switching power (

Logic locking has emerged as a prominent technique to protect an integrated circuit from piracy, overbuilding, and hardware Trojans. Most of the well-known logic locking techniques are vulnerable to satisfiability (SAT) based attack. Though several SAT-resistant logic locking techniques such as Anti-SAT block (ASB) are reported that increase the time to decipher the secret key, the existing techniques are either vulnerable to signal probability skew (SPS) based removal attack or require significant design overhead. Therefore, a new lightweight ASB design and obfuscation technique is proposed that effectively integrate and obfuscates the ASB in the design to thwart removal attack. We first propose a new ASB design/integration approach that effectively thwarts the structural/functional analysis based removal attack with minimum overhead. Further, we also propose an ASB obfuscation approach that shifts the inverter deep in the circuit using De Morgan's law and replaces an ASB gate with a key-gate to thwart SPS based removal attack. Moreover, a new algorithm is proposed that inserts the ASB in the locked design to achieve desired output corruptibility. Finally, a new INV/BUFF key-gate is proposed that constructs the ASB with reduced overhead over the XOR/XNOR. Experimental evaluation on ISCAS-85 benchmarks shows that our ASB design and obfuscation approaches, on an average, reduce area overhead by 25.5% and 22% respectively, and effectively prevent removal attack without reducing any security.

Electronic Boolean logic gates, the foundation of current computation and digital information processing, are reaching final limits in processing power. The primary obstacle is energy consumption which becomes impractically large, > 0.1 fJ/bit per gate, for signal speeds just over several GHz. Unfortunately, current solutions offer either high-speed operation or low-energy consumption. We propose a design for Boolean logic that can achieve both simultaneously (high speed and low consumption), here demonstrated for NOT and XNOR gates. Our method works by passively modifying the phase relationships among the different frequencies of an input data signal to redistribute its energy into the desired logical output pattern. We experimentally demonstrate a passive NOT gate with an energy dissipation of ~1 fJ/bit at 640 Gb/s and use it as a building block for an XNOR gate. This approach is applicable to any system that can propagate coherent waves, such as electromagnetic, acoustic, plasmonic, mechanical, or quantum., Typically, Boolean logic gates have to compromise between high speed and low energy consumption which can become limiting at scale. Here, the authors demonstrate architectures for NOT and XNOR gates that enable simultaneous low power and fast operation.

In this paper, we reported a reflective semiconductor optical amplifier (RSOA), in which the input light propagates and reflects back to the input port after amplifying twice through its active reg...

In this paper, a new method for implementing all two-input logic gates on an identical single-stage structure is proposed. We have used unique characteristics of single-electron transistors, which have periodic output–input relation, to design the gates and implement all two-input logic gates (symmetric/non-symmetric, monotonic/non-monotonic) by a single-stage design including only one single-electron transistor. In conventional monotonic devices, such as BJTs and MOSFETs, implementing non-monotonic logic gates such as XOR and XNOR is impossible with a single-stage circuit and a multistage design is required which leads to more complexity, more chip area and higher power consumption. We present the proposed methodology at first, and then, the details of the designs are investigated. The results are obtained analytically using a new approach named two-potential and then confirmed by numerical methods. Furthermore, important characteristics of the proposed gates such as maximum operating temperature, speed of the gates and frequency limitations, power consumption (static and dynamic) and scaling to other technologies have been investigated. Finally, a general idea has been presented about the application of the introduced approach and gate structures in the field of logic circuit and system designing.

Microring resonator (MRR) is regarded as one of the most widely-used building blocks in photonic integration, which is employed to implement optical filtering, routing, sensing, true time delay, signal processing, logic operations and so on. However, a single MRR intrinsically produces Lorentzian or Lorentzian-derivative shape responses with very sharp peaks, which is incapable of handling wideband signals for microwave photonic systems. In this paper, we introduce a reflective-type MRR with a reflector connected to the drop port of an add-drop MRR. Thanks to the reflector, reconfigurable intensity and group delay responses can be achieved by setting the coupling coefficients of the MRR, leading to the implementation of flat-top filtering, wideband optical true time delay, XNOR/XOR optical logic operation and electro-optic modulation. Both theoretical analysis and experimental demonstration are carried out. This new MRR structure may enable a new, compact and low-cost design strategy for the integrated reconfigurable or programmable microwave photonic systems.

An associative memory is a special type of artificial neural network that has the purpose of store input patterns with their corresponding output patterns and efficiently recall a pattern from a noise-distorted version. Presented in this article is a new framework for constructing a binary associative memory model based on two new autoinverse operations called extended XOR/XNOR; these new operations are generated from the XOR/XNOR operations, respectively. Two types of associative memory are generated with this model: the max type (XOR-AM max), which is constructed with the maximum of the extended XOR operation, and the min type (XOR-AM min), which is constructed with the minimum of the extended XNOR operation. The XOR-AM max exhibits tolerance against the presence of patterns distorted by dilative noise, whereas the XOR-AM min exhibits tolerance against the presence of patterns distorted by erosive noise; both types of memory converge in a single step, use the same extended XOR/XNOR operator for learning and recalling phases, operate in heteroassociative and autoassociative modes, and show infinite storage capacity for the autoassociative mode. Finally, computer simulation results are presented for the new memories based on the extended XOR/XNOR (XOR-AM), which have better or equal performance compared to other associative memories. For the experiments with mixed noise, the conditions established by the kernel method proposed by Ritter for Morphological Associative Memories were conserved, and the solution algorithm proposed by Hattori for the construction of the kernel patterns of these memories was modified.

Hybrid logic style is widely used to implement full adder (FA) circuits. Performance of hybrid FA in terms of delay, power, and driving capability is largely dependent on the performance of xor–xnor circuit. In this article, a high-speed, low-power 10-T xor–xnor circuit is proposed, which provides full swing outputs simultaneously with improved delay performance. The performance of the proposed circuit is measured by simulating it in cadence virtuoso environment using 90-nm CMOS technology. The proposed circuit reduces the power delay product (PDP) at least by 7.5% than that of the available xor–xnor modules. Four different designs of FAs are also proposed in this article utilizing the proposed xor–xnor circuit and available sum and carry modules. The proposed FAs provide 2%–28.13% improvement in terms of PDP than that of other architectures. To measure the driving capabilities, the proposed FAs are embedded in 2-, 4-, and 8-bit cascaded full adder (CFA) structures. Results show that two of the proposed FAs provide the best performance for a higher number of bits among all the FAs.

The digital designs operating in sub/near-threshold region are susceptible to timing errors due to the extreme impact of process, voltage, and temperature (PVT) variations. This paper proposes a new error-detecting latch (EDL) to mitigate the impact of PVT variations. The proposed EDL is a single-phase clocked design, which significantly reduces the clock power consumption of the design. The proposed EDL follows a merged and shared architecture of two latches along with an XNOR gate, which leads to a compact layout of EDL. The post-layout simulations in an industrial 28 nm CMOS technology node, show a minimum clock power savings of 31%, average power savings of 16%, and reduction in leakage power by 23% in comparison to the state-of-the-art EDLs at 0.4 V. The 10K rigorous Monte-Carlo simulations across the supply voltage range of 0.23 V - 0.8 V and clock frequency range of 1.6 MHz - 70 MHz shows that the proposed EDL is tolerant to leakage-induced false errors and glitches. SSEDL is robust to process variations even with minimum-sized transistors.

In VLSI system design, one of the most significant areas of on-going research is high speed with low power system design. Usually the speed of the VLSI circuits like binary adders can be improved by more parallelism but, this more parallelism idea will increase the power consumption and area of the circuit. Therefore there is a trade-off between speed and power/area. A carry select adder is one of the fast binary adders but it consumes more power and area. In this paper, we proposed a low power and area efficient and high speed binary carry select adder (CSLA). The half sum and carry generator (HSCG) of the proposed CSLA is designed with a new methodology, that the HSCG output are estimated using input A and B not with carry-in hence it is faster and results in less area leads to low power consumption. Moreover, the NAND gate based circuit is used to compute the intermediate carries within the block and carry-out of the block which are derived from HSCG output along with carry-in. Similarly, the full sum of the proposed adder is generated from XNOR gate based circuitry by utilizing the intermediate carries of the block. The existing and proposed CSLAs are synthesized with the Synopsys EDA tool using 32 nm CMOS technology. The performance of the existing and proposed designs are analyzed and the results shows that the proposed 64-bit CSLA exhibits average reduction of 43% in power and average of 25% less utilization in terms of area compared to existing design. This proposed CSLA is used in a FIR Filter and obtained significant reduction in ADP and PDP.

All-optical signal processing in optical technology is the most reliable process that mitigates the limitations of speed and processing power in electronics by replacing the electronic components with the equivalent optical switching components. All-optical switches are very important in communication and computing, as most communication around the globe is carried on optical fibers. Optical switching is effectively performed in high data rate systems through all-optical gates. The nonlinear signal processing in semiconductor optical amplifier (SOA) is the key element for implementing various optical gate logics. In this paper, combination of optical gates such as all-optical AND, OR, NOT, XOR, NOR and XNOR operations are successfully simulated in single structure. The performance analysis of each gate and its cascaded feature is analyzed by varying the structural and functional parameters of SOA’s active region. The simulation results confirm that the proposed design can be implemented at high data rate of more than 10Gbps with good quality factor and extinction ratio of around 12 dB.