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The proposed Circular Electron Positron Collider (CEPC) imposes new challenges for the vertex detector in terms of pixel size and material budget. A Monolithic Active Pixel Sensor (MAPS) prototype called TaichuPix, based on a column drain readout architecture, has been developed to address the need for high spatial resolution. In order to evaluate the performance of the TaichuPix-3 chips, a beam test was carried out at DESY II TB21 in December 2022. Meanwhile, the Data Acquisition (DAQ) for a multi-plane configuration was tested during the beam test. This work presents the characterization of the TaichuPix-3 chips with two different processes, including cluster size, spatial resolution, and detection efficiency. The analysis results indicate the spatial resolution better than 5 µm and the detection efficiency exceeding 99.5 % for TaichuPix-3 chips with the two different processes. [ABSTRACT FROM AUTHOR]

The proposed Circular Electron Positron Collider poses significant challenges for the vertex detector in terms of material budget, spatial resolution, readout speed, and power consumption. To address these challenges, a Monolithic Active Pixel Sensor prototype, named TaichuPix, has been developed based on a column drain readout architecture. The performance of the second version of this prototype, TaichuPix2, has been evaluated using a radioactive source, which exhibits a time walk of less than 100 ns corresponding to the threshold of 380 e − and amplitude variation of analog output from 300 mV to 500 mV. An infrared laser setup is utilized to estimate the single-point spatial resolution of this sensor for minimum-ionizing particles. The setup includes a high-precision three-dimensional translation stage and an optical system with a 1064 nm laser diode. With this setup, the spatial resolution is estimated to be about 4 µm. The performance for real particles is to be confirmed in a test beam. [ABSTRACT FROM AUTHOR]

Advanced synchrotron radiation sources are major facilities for analyzing the formation and evolution of material structure in multidisciplinary research, owing to their high luminosity, low emittance, wide energy bandwidth and other characteristics. In China, several advanced synchrotron radiation sources are under construction, including the HEPS (High Energy Photon Source) and SHINE (Shanghai high repetition rate X-ray Free Electron Laser and extreme light facility). These facilities are poised to become major multidisciplinary research platforms in China. To meet the requirements of pixel detectors in these facilities, dedicated pixel readout chips are being developed, including HEPS-BPIX and HYLITE. This paper presents a high-speed serializer circuit developed in a commercial 130-nm CMOS technology for the full-scale (128 × 128) pixel readout chip of HYLITE, which requires a data rate of 4 Gbps currently. The serializer consists of a 16-to-1 binary-tree multiplexer, a ring-oscillating-based phase-locked loop (RO-PLL) and a current-mode logic driving stage with a multi-stage pre-amplifier. Test results demonstrate its expected functionality within a wide operating range from 0.52 Gbps to 5.5 Gbps. At 5.12 Gbps, the measured jitter values are about 2 ps for random jitter, 20 ps for deterministic jitter, and 47 ps for total jitter with a 10−12 bit error rate. Additionally, the horizontal and vertical eye openings are 0.84 UI and 72%, respectively. These positive results indicate that the serializer meets the requirements of HYLITE. [ABSTRACT FROM AUTHOR]

Monolithic Active Pixel Sensor is one of the promising candidates for the Circular Electron Positron Collider Vertex detector, due to its good performance and trade-off of granularity, readout speed, material budgets and power consumption. A full-scale TaichuPix chip, including a matrix of 512 × 1024 pixels with a size of 25 × 25 μm2 is developed to provide a spatial resolution better than 5 μm. It requires a raw data rate up to 3.84 Gbps and power consumption less than 100 mA for the serializer circuit. Based on one of the small-scale prototypes, the highest serial data rate is tested to be 3.36 Gbps with a peak-to-peak jitter of about 150 ps and large current consumption. Moreover, the 32-bit parallel data width of the serializer isn't suitable for the 8B10B encoder. Therefore, two 4 Gbps serializers have been designed and optimized to meet these requirements based on the same process node of 180 nm as the TaichuPix, considering the funding and time costs. The serializer consists of a phase locked loop (PLL), several 5:1 sub-multiplexers based on a shift-register chain, a 4:1 or 8:1 sub-multiplexer based on the binary-tree structure, a clock distributor and a high-speed driver. Both ring-oscillating PLL and LC-tank PLL were integrated for performance evaluation. The preliminary tests showed low-jitter characteristics of the two PLLs despite this version's biasing problem, and both serializer circuits functioned correctly. A revision corrected the error and was submitted in October 2023. [ABSTRACT FROM AUTHOR]

The AC-coupled Strip LGAD (Strip AC-LGAD) is a novel LGAD design that diminishes the density of readout electronics through the use of strip electrodes, enabling the simultaneous measurement of time and spatial information. The Institute of High Energy Physics has designed a long Strip AC-LGAD prototype with a strip electrode length of 5.7 mm and pitches of 150 μ m, 200 μ m, and 250 μ m. Spatial and timing resolutions of the long Strip AC-LGAD are studied by pico-second laser test and beta source tests. The laser test demonstrates that spatial resolution improves as the pitch size decreases, with an optimal resolution achieved at 8. 3 μ m. Furthermore, the Beta source test yields a timing resolution of 37.6 ps. [ABSTRACT FROM AUTHOR]

Background: Dysfunction of long noncoding RNA (lncRNA) is associated with tumorigenesis of various malignancies, including glioma. LncRNA RGMB-AS1 (RGMB antisense RNA 1) has been reported to participate in initiation and progression of several cancers, such as lung cancer, hepatocellular carcinoma and laryngeal squamous cell carcinoma. Nevertheless, whether RGMB-AS1 regulates glioma development is not investigated. In this study, we aimed to determine its roles in glioma. Methods: qRT-PCR and Western blotting were used to measure gene expression. CCK8 and colony formation assays were utilized to analyze proliferation. Transwell assay was used to determine cell migration and invasion. Luciferase reporter assay was used to validate the interactions among RGMB-AS1, miR-1200 and HOXB2. Results: RGMB-AS1 was upregulated in glioma tissues and associated with glioma grade and patients' prognosis. Moreover, RGMB-AS1 silencing significantly inhibited the proliferation, migration and invasion of glioma cells. RGMB-AS1 downregulation led to more tumor cells arrested in the quiescent state. Mechanistically, we found that RGMB-AS1 was a molecular sponge for miR-1200. MiR-1200 level was inhibited by RGMB-AS1. And RGMB-AS1 promoted HOXB2 expression via sponging miR-1200. Restoration of HOXB2 effectively rescued the abilities of proliferation, migration and invasion in RGMB-AS1-depleted glioma cells. Conclusion: Collectively, our work clarified that RGMB-AS1/miR-1200/HOXB2 signaling exerts an essential role in regulating glioma progression. [ABSTRACT FROM AUTHOR]

Oxidation time and exfoliated conditions of graphite oxides (GOs) were investigated to prepare few–layer graphene oxide and reduced graphene oxide via a modified Hummers approach. Different oxidative degree of GOs was prepared by changing oxidation time, and the effects of oxidative degree of GOs in different oxidation time were studied by XRD, FT-IR. Afterwards, highly oxidized GOs were used as precursor to prepare graphene oxide and reduced graphene oxide by ultrasonic dispersion method and thermal expansion method. The exfoliated conditions (ultrasonic power and ultrasonic time, thermal exfoliated temperature) were investigated to prepare few-layered graphene oxide and reduced graphene oxide. [ABSTRACT FROM AUTHOR]

The proposed Circular Electron Positron Collider (CEPC) imposes new challenges for the vertex detector in terms of material budget, spatial resolution, readout speed, and power consumption. It is necessary to design and construct the CEPC vertex detector with state-of-the-art silicon detector technologies. A dedicated CMOS Pixel Sensor chip, named TaichuPix, is being developed for the first 6-layer CEPC vertex detector prototype. The TaichuPix development is based on a fast in-pixel readout combined with a hit-driven architecture, which would be beneficial for the high hit rate. This work reports the requirements for the sensor and the design approach being followed to cope with it. Two small-scale prototypes (25 mm2) capable of achieving a hit rate up to 36 MHz/cm2, were designed in a 180 nm CMOS process. One of them, the TaichuPix-2 prototype was characterized with electrical and radioactive sources in the laboratory. The test results on the chip functionality and the pixel performance in terms of threshold and noise as well as the timing response are reported. [ABSTRACT FROM AUTHOR]