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Metal-oxide-semiconductor capacitors embedded with the Si16Sb84 nanocrystals have been fabricated and studied for their charge trapping, detrapping, and retention characteristics. Si16Sb84 NCs were achieved by annealing at 250°C.Both holes and electrons can be trapped to the nanocrystal-embedded dielectric stack depending on the polarity of the applied gate voltage. Charges trapped to the NCs, which are not observed in the control sample. More than half of the originally trapped charges can be retained in the embedded NCs for more than 10 yr. The nanocrystalline Si16Sb84 embedded in MOS capacitors is useful for this nonvolatile memory device.

The dry etching characteristic of new Ti0.5Sb2Te3(TST) phase change material was investigated by using the CF4 and Ar gas mixture. The research mainly focuses on how to optimize the experimental parameters such as gas flow rate within the chamber, CF4 /Ar flow ratio, the chamber background pressure and the incident RF power applied to the lower electrode. The results show that CF4 mainly plays a role of chemical etching and Ar plays a role of physical bombardment. The etching rate of TST films increases with the increasing concentration of CF4 in the gas mixture. The etching chamber pressure has less effect on the TST film etching speed, while the etching power has larger effect. The etch rate is up to 126 nm/min with the smooth etched surface(RMS=0.82 nm) and TST film profile is almost vertical(approaching 90°) using optimized etching parameters, including the total flow rate of 50 sccm, CF4 concentration of 26%, power of 400 W and pressure of 13.3 Pa.

Recently, nanocrystal nonvolatile memory (NVM) devices using nanocrystals (NCs) have attracted great research interest. In this work, we investigated the feasibility of Ni nanocrystals embedded in metal oxide semiconductor (MOS) capacitor structure for NV

National Integrate Circuit Research Program of China [2009ZX02023-3]; National Basic Research Program of China [2007CB935400, 2010CB934300, 2006CB302700]; National High Technology Development Program of China [2008AA031402]; Science and Technology Council

Structures of nanocrystalline-Si (nc-Si) sandwiched between two asymmetric ultrathin SiO2 layers were fabricated. The nc-Si (dot density of 1011 cm−2) was formed by decomposition of hydrogen-diluted silane and the ultrathin SiO2 layers (about 2 nm) were prepared by plasma oxidation at a lower temperature (250 degrees C). The whole fabrication processes were completed in situ in a plasma-enhanced chemical vapour deposition system. By using the capacitance–voltage (C–V) and conductance–voltage (G–V) spectroscopy, we studied the electronic properties of the annealed samples. The experimental results show that there are distinct capacitance peaks and conductance plateau or peaks for annealed samples at room temperature, which can be explained by direct tunnelling of electrons into the nc-Si. At the same time, Coulomb blockade plays an important role in the electronic transport in the nc-Si. The effect of thermal annealing in N2 ambient on the electronic properties was studied and the results indicate that high temperature (1000 degrees C) annealing can improve the size uniformity of the nc-Si prepared by decomposition of hydrogen-diluted silane.

We report the experimental phenomenon of large resistance change in plasma oxidized TiOx/TiNx film fabricated on W bottom-electrode-contact (W-BEC) array. The W-BEC in diameter 260?nm is fabricated by a 0.18??m CMOS technology, and the TiOx/TiNx cell array is formed by rf magnetron sputtering and reactive ion etching. In current?voltage (I?V) measurement for current-sweeping mode, large snap-back of voltage is observed, which indicates that the sample changes from high-resistance state (HRS) to low-resistance state (LRS). In the I?V measurement for voltage-sweeping mode, large current collapse is observed, which indicates that the sample changes from LRS to HRS. The current difference between HRS and LRS is about two orders. The threshold current and voltage for the resistance change is about 5.0?10?5?A and 2.5?V, respectively. The pulse voltage can also change the resistance and the pulse time is as shorter as 30?ns for the resistance change. These properties of TiOx/TiNx film are comparable to that of conventional phase-change material, which makes it possible for RRAM application.

Ge1Sb2Te4-based chalcogenide random access memory array, with a tungsten heating electrode of 260 nm in diameter, is fabricated by 0.18-μm CMOS technology. Electrical performance of the device, as well as physical and electrical properties of Ge1Sb2Te4 thin film, is characterized. SET and RESET programming currents are 1.6 and 4.1 mA, respectively, when pulse width is 100 ns. Both the values are larger than those of the Ge2Sb2Te5-based ones with the same structure and contact size. Endurance up to 106 cycles with a resistance ratio of about 100 has been achieved.

In order to reduce the reset current of chalcogenide random access memory, a W sub-microtube heater electrode with outer/inner diameter of 260/100 nm, which was fabricated with standard 0.18-μm technology, is proposed for the first time to achieve a reset current of about 0.5 mA. The reasons may be that sub-microtube increases the number of electrode edge and thermal efficiency is improved greatly because the thermal density on the edge of sub-microtube electrode is generally the highest.

Phase change memory (PCM) cell array is fabricated by a standard complementary metal–oxide–semiconductor process and the subsequent special fabrication technique. A chalcogenide Ge2Sb2Te5 film in thickness 50 nm deposited by rf magnetron sputtering is used as storage medium for the PCM cell. Large snap-back effect is observed in current–voltage characteristics, indicating the phase transition from an amorphous state (higher resistance state) to the crystalline state (lower resistance state). The resistance of amorphous state is two orders of magnitude larger than that of the crystalline state from the resistance measurement, and the threshold current needed for phase transition of our fabricated PCM cell array is very low (only several μA). An x-ray total dose radiation test is carried out on the PCM cell array and the results show that this kind of PCM cell has excellent total dose radiation tolerance with total dose up to 2×106 rad(Si), which makes it attractive for space-based applications.

Novel Si3.5Sb2Te3 phase change material for phase change memory is prepared by sputtering of Si and Sb2Te3 alloy targets. Crystalline Si3.5Sb2Te3 is a stable composite material consisting of amorphous Si and crystalline Sb2Te3, without separated Te phase. The thermally stable Si3.5Sb2Te3 material has data retention ability (10 years at 412K) better than that of the Ge2Sb2Te5 material (10 years at 383 K). Phase change memory device based on Si3.5Sb2Te3 is successfully fabricated, showing low power consumption. Up to 2.2 × 107 cycles of endurance have been achieved with a resistance ratio lager than 300.

An MOS (metal oxide semiconductor) capacitor structure with double-layer heterogeneous nanocrystals consisting of semiconductor and metal embedded in a gate oxide for nonvolatile memory applications has been fabricated and characterized. By combining vacuum electron-beam co-evaporated Si nanocrystals and self-assembled Ni nanocrystals in a SiO2 matrix, an MOS capacitor with double-layer heterogeneous nanocrystals can have larger charge storage capacity and improved retention characteristics compared to one with single-layer nanocrystals. The upper metal nanocrystals as an additional charge trap layer enable the direct tunneling mechanism to enhance the flat voltage shift and prolong the retention time.

We realized the fabrication of 2D ordered arrays of CdS nanocrystals by nanosphere lithography by use of a monolayer of self-assembled polystyrene spheres 220nm in diameter as a mask. We used scanning electron microscope (SEM) to characterize the structure of samples. The results indicate that the 2D arrays of CdS nanocrystals produced by nanosphere lithography have highly ordered structure which has the same period of the original PS mask. According to the transmission spectrum，it is estimated that the forbidden band width of the CdS nanocrystals is around 2.60eV，which shows a size-dependence of the CdS nanocrystals. This structure has the promising application in the light filter and single-photon emitter.

Doubly stacked layers of amorphous silicon (a-Si) between amorphous silicon nitride (a-SiNx) layers have been fabricated by plasma enhanced chemical vapor deposition (PECVD)technique. Si nanocrystal (nc-Si) layers were formed by thermal crystallization of a-Si layers after a furnace annealing at 1100℃ for 30 min in N2 ambient. The phenomena of charge trapping and storage in nc-Si layers were observed in both capacitance-voltage (C-V) and current-voltage (I-V) measurements at room temperature. The structure has revealed a double-level charging process. Two stages of charge storage were evident in the series of C-V curves. The phenomena and mechanism of charge storage were discussed in detail.