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With the scaling of lateral dimensions in advanced transistors, an increased gate capacitance is desirable both to retain the control of the gate electrode over the channel and to reduce the operating voltage1. This led to a fundamental changein the gate stack in 2008,the incorporation of high-dielectric-constant HfO2(ref.2), which remains the material of choiceto date. Here we report HfO2-ZrO2 superlattice heterostructures as a gate stack, stabilized with mixed ferroelectric-antiferroelectric order, directly integrated onto Si transistors, and scaled down to approximately 20 ångströms, the same gate oxide thickness required for high-performance transistors. The overall equivalent oxide thickness in metal-oxide-semiconductor capacitors is equivalent to an effective SiO2 thickness of approximately 6.5 ångströms. Such a low effective oxide thickness and the resulting large capacitance cannot be achieved in conventional HfO2-based high-dielectric-constant gate stacks without scavenging the interfacial SiO2, which has adverse effects on the electron transport and gate leakage current3. Accordingly, our gate stacks, which do not require such scavenging, provide substantially lower leakage current and no mobility degradation. This work demonstrates that ultrathin ferroic HfO2-ZrO2 multilayers, stabilized with competing ferroelectric-antiferroelectric order in the two-nanometre-thickness regime, provide a path towards advanced gate oxide stacks in electronic devices beyond conventional HfO2-based high-dielectric-constant materials.

Analog and RF mixed-signal cryogenic-CMOS circuits with ultrahigh gain-bandwidth product can address a range of applications such as interface circuits between superconducting (SC) single-flux quantum (SFQ) logic and cryo-dynamic random-access memory (DRAM), circuits for sensing and controlling qubits faster than their decoherence time for at-scale quantum processor. In this work, we evaluate RF performance of 18 nm gate length ( $L_{G}$ ) fully depleted silicon-on-insulator (FDSOI) NMOS and PMOS from 300 to 5.5 K operating temperature. We experimentally demonstrate extrapolated peak unity current-gain cutoff frequency ( $f_{T}$ ) of 495/337 GHz ( $1.35\times /1.25\times $ gain over 300 K) and peak maximum oscillation frequency ( $f_{\mathrm {MAX}}$ ) of 497/372 GHz ( $1.3\times $ gain) for NMOS/PMOS, respectively, at 5.5 K. A small-signal equivalent model is developed to enable design-space exploration of RF circuits at cryogenic temperature and identify the temperature-dependent and temperature-invariant components of the extrinsic and the intrinsic FET. Finally, performance benchmarking reveals that 22 nm FDSOI cryogenic RF CMOS provides a viable option for achieving superior analog performance with giga-scale transistor integration density.

Cryogenic CMOS is a crucial component in building scalable quantum computers, predominantly for interface and control circuitry. Further, high-performance computing can also benefit from cryogenic boosters. This necessitates an in-depth understanding of the power and performance trade-offs in the cryogenic operation of digital logic. In this article, we analyze digital standard cells in a 28 nm high- $k$ metal gate (HKMG) CMOS foundry process design kit (PDK). We have developed Berkeley Short-channel IGFET Model (BSIM)4 of cryogenic CMOS and calibrated them with experimental measurements. Since low-temperature operation leads to an exponential decrease in the leakage current of the transistors, we further tune the threshold voltage of the devices to achieve iso-leakage. In this article, we present inverter static and dynamic characteristics and multiple ring oscillator (RO) structures. The simulation study shows that we can achieve 28% (FO4-RO) – 59% (NAND3-RO) higher performance under iso- $V_{\mathrm {DD}}$ scenario and up to 90% improvement in the energy-delay product (EDP) under iso-overdrive scenario at 6 K compared to room temperature.

Advances in the theory of semiconductors in the 1930s in addition to the purification of germanium and silicon crystals in the 1940s enabled the point-contact junction transistor in 1947 and initiated the era of semiconductor electronics. Gordon Moore postulated 18 years later that the number of components in an integrated circuit would double every 1 to 2 years with associated reductions in cost per transistor. Transistor density doubling through scaling—the decrease of component sizes—with each new process node continues today, albeit at a slower pace compared with historical rates of scaling. Transistor scaling has resulted in exponential gain in performance and energy efficiency of integrated circuits, which transformed computing from mainframes to personal computers and from mobile computing to cloud computing. Innovations in new materials, transistor structures, and lithographic technologies will enable further scaling. Monolithic 3D integration, design technology co-optimization, alternative switching mechanisms, and cryogenic operation could enable further transistor scaling and improved energy efficiency in the foreseeable future.

We experimentally demonstrate back-end-of-the-line (BEOL) compatible ( ${I}_{D{,SAT}}$ of $370~\mu \text{A}/\mu \text{m}$ , and on–off ratio $> 4\times 10^{9}$ at ${V}_{DS} = 1$ V and ${V}_{GS}$ – ${V}_{TH}= 2$ V. We identify fundamental transport mechanisms that limit electron mobility in amorphous IWO transistors at different gate-bias ( ${V}_{GS}$ ) and temperature. Benchmarking reveals that amorphous IWO FETs are promising candidate for in situ transistor fabrication in the BEOL for enabling high-performance monolithic 3-D (M3-D) integrated circuits.

The electronic transport properties of amorphous In$_{2} \mathrm{O}_{3}(\mathrm{a} - In _{2} \mathrm{O}_{3})$ are investigated from first principles simulations for BEOL transistor application. It is determined that local atomic and electronic structure disorders in a-In 2 O 3 are the fundamental origin of reduced mobility in amorphous phase. Medium range order In-In connectivity is responsible for the electron conduction pathway. It is found that amorphous disorder present in a-In 2 O 3 could induce shallow donor states and acceptor states that are responsible for the device threshold voltage instability. Nonstoichiometric defects including indium vacancy and interstitial will further increase the density of these defect states intrinsic to a-In 2 O 3 . The results could provide a better understanding of the electronic transport behavior in a-In 2 O 3 and useful insights for future defect controlling for better device performance.

Compute-in-memory has received a lot of research interests recently to implement the data-intensive computation in deep neural networks. By performing the computing at the storage location, CIM avoids the excessive data transfer thus improving the energy efficiency. SRAM based CIM is one of the promising candidates for its mature technology availability at advanced technology node. To further speed up for CMOS circuits, cryogenic computing which operates at low temperatures has emerged as an attractive solution for highperformance computing at the data center. In this work, we modified NeuroSim, a device-to-system modelling framework with experimentally calibrated 28nm transistor parameters from room temperature to 4K Then we benchmark the performance of SRAM based CIM for ResNet-18 on ImagNet dataset. The energy-delay-product is compared across the temperature, revealing the performance and energy efficiency boost by cryogenic computing. When the cooling infrastructure cost is considered, the overall energy benefits are overshadowed though.

With the scaling of lateral dimensions in advanced transistors, an increased gate capacitance is desirable both to retain the control of the gate electrode over the channel and to reduce the operating voltage

Even at deep cryogenic temperature ~20 milli-Kevin, the qubit is fragile, therefore a feedback loop is needed to perform the quantum error correction (QEC). It is highly desirable to operate the QEC at 4K to minimize the thermal heat transfer between the physical qubits and the peripheral control circuitry. In this work, we propose implementing the surface code QEC circuitry with compute-in-memory (CIM) based recurrent neural network accelerator at 4K. To serve this purpose, we develop Cryo-NeuroSim, a device-to-system modeling framework that calibrate the transistor and interconnect parameters with experimental data at cryogenic temperature. Then we benchmark the QEC circuitry with SRAM technologies and optimize its energy-delay-product (EDP) with reengineered threshold voltage and supply voltage.

In this work, we evaluate the role of polarization switching and charge trapping in the operation of ferroelectric FET (FeFET) through combined experimental characterization and comprehensive modeling. We are demonstrating that: 1) the significant charge gap in the quasi-static split-CV (QSCV) and small signal CV is fundamental and not indicative of trapped charge density. This is because the QSCV senses the irreversible polarization switching while the small signal CV mainly probes the reversible domain wall displacement under ac excitation, theoretically yielding different scales of charge response in the two measurements. 2) Trapped charge density during memory write can be inferred from the measured charge release dynamics with the help of a comprehensive FeFET model that incorporates both the polarization switching and the charge trapping and release dynamics.

We demonstrate, for the first time, monolithic 3D (M3D) integration of back-end-of-line (BEOL) compatible Hf 0.5 Zr 0.5 O 2 (HZO) ferroelectric FET (FeFET) with front-end-of-line (FEOL) high-k/metal gate (HKMG) Si-NMOS. We use low thermal budget ( 2 O 3 (IWO) semiconducting oxide channel and demonstrate high remnant polarization charge density 2P R , of 40μC/cm2 reliable with switching characteristics. We report (a) read memory window of 0.45V in ultra-scaled 20nm channel length IWO FeFET, (b) write speed of 100ns, and (c) write endurance >108 cycle. We further demonstrate a 2bit/cell synaptic weight cell with well separated conductance states. System-level analysis of compute-in-memory (CIM) accelerators for performing inference on CIFAR-10 image dataset using VGG-8 model shows that 22nm BEOL FeFET achieves 3× higher energy-efficiency than 7nm SRAM while occupying a smaller memory array area due to area folding enabled by M3D architecture.

This paper presents 3D NeuroSim, a benchmark framework of monolithic 3D (M3D) integrated compute-in-memory (CIM) accelerators. To address the challenges of analog-to-digital converter (ADC) overhead and scaling limitations caused by high write voltage in emerging nonvolatile memory (eNVM), we propose partitioning the circuit modules in hybrid technology nodes across two stacked tiers with massive inter-tier vias. This framework features versatile back-end-of-line (BEOL)-compatible transistors, including laser-recrystallized silicon transistor and oxide transistor, and analyzes the thermal profile for M3D integration. Finally, we benchmark the CIM accelerators for VGG-8 on CIFAR-10 and reveal the substantial benefits in energy efficiency of a hybrid M3D architecture (45nm eNVM array+7nm ADC and logic).

In this work, we developed a comprehensive model for ferroelectric FET (FeFET), which can capture all the essential ferroelectric behaviors. Unlike previous models, which can describe only a subset but not all the reported ferroelectric behaviors, the proposed model can: i) predict device performance with geometry scaling; ii) quantify the device-to-device variation with device scaling; iii) exhibit stochasticity during a single domain switching; and iv) capture the accumulation of domain switching probability with applied pulse trains. This comprehensive model would enable researchers to explore a wide range of FeFET applications and guide device development, optimization and benchmarking.

We experimentally demonstrate BEOL compatible ( $\mathrm{I}_{\mathrm{D},\mathrm{SAT}}$ of $370\mu\mathrm{A}/\mu\mathrm{m}$ , and on-off ratio> 4×109 at $\mathrm{V}_{\mathrm{DS}} =1\mathrm{V}$ and $\mathrm{V}_{\mathrm{GS}}-\mathrm{V}_{\mathrm{T}}=2\mathrm{V}$ We provide insight into the electrostatic gate control efficiency through temperature and frequency dependent admittance measurement. We identify fundamental transport mechanisms that limit electron mobility inamorphous IWO as a function of gate-bias $(\mathrm{V}_{\mathrm{GS}})$ and temperature. Benchmarking shows that IWO DGFET is a promising BEOL transistor for enabling high-performance monolithic three-dimensional (M3D) integrated circuits.

High static power associated with static random access memory (SRAM) represents a bottleneck in increasing the amount of on-chip memory. Novel, emerging nonvolatile memories such as spin-transfer torque magnetic random access memory (STT-RAM), resistive random access memory (RRAM), and ferroelectric field effect transistor-based random access memory (FeFET-RAM) are alternatives for replacing hardware kernels such as SRAM-based last level caches (LLC) due to their fast access times and lower leakage. In this paper, we study an ultra-dense FeFET-RAM based on 1-FeFET memory cells, and address potential disturbance issues at the array level. Disturbances are studied experimentally and via simulation. Experimental measurements are well correlated with modeling results suggesting that we have a good understanding of how disturbance issues will manifest themselves. That said, previous WRITE schemes for 1-FeFET arrays may: 1) exacerbate disturbances and 2) significantly degrade figures of merit (FoM) such as WRITE power. To address these issues, we propose the use of columnwise body connections to simultaneously overcome disturbances and reduce leakage currents during WRITES. We present detailed studies on how 1-FeFET memory cells and arrays (with columnwise body bias) fare when compared to traditional SRAM approaches and other emerging technologies. Notably, we benchmark the 1-FeFET memory against 1T * 1FeFET and 2T * 1FeFET designs proposed in early works, as well as SRAM, STT-RAM, and RRAM. Our evaluation of a $64\times 64$ FeFET-RAM array shows that the area, READ delay, and static power are reduced by $\sim 5.3\times $ , $\sim 1.5\times $ , and $\sim 74\times $ , respectively, when compared to an SRAM equivalent. Also, the 1-FeFET memory cell design shows $\sim 50\times $ improvements in terms of WRITE energy with respect to STT-RAM and RRAM counterparts.

28nm Gate First High-K Metal Gate (GF-HKMG) technology is analyzed for Hot-Carrier Degradation (HCD) under varying gate/drain (V G /V D ) bias and temperature (T: 300K to 77K). A compact model is used to partition measured threshold voltage shift (ΔV T ) into interface trap generation due to pure HCD (ΔV IT-HC ), Bias Temperature Instability (BTI, ΔV IT-BT ), and electron/hole trapping (ΔV ET /ΔV HT ) subcomponents. The relative importance of the subcomponents is analyzed for varying T. Although pure HCD dominates under Cryo-CMOS operation, the T dependence is shown to be different for Si NMOS and SiGe PMOS FETs. Finally, the impact on the circuit (RO: Ring Oscillator) operation is analyzed.

We demonstrate a novel strategy to scaling the equivalent oxide thickness (EOT) of MOSFETs by tuning the composition of Hf 1-x Zr x O 2 thin-film near morphotropic phase boundary (MPB) between orthorhombic ferroelectric phase and tetragonal anti-ferroelectric phase. This approach can avoid the shortcomings of mobility and reliability degradation incurred in interlayer (IL) scaling approach and gate leakage increase from band gap reduction in traditional higher κ materials. Through comprehensive theoretical modeling and experimental characterization, we show that: 1) MPB exists in Hf 1-x Zr x O 2 system due to phase transformation from orthorhombic phase to tetragonal phase with the increase of Zr concentration, in order to reduce the dipole-dipole interaction energy between the oxygen sub-lattices under compression; 2) κ is maximum (κ=38) near the MPB around 70% Zr as two phases co-exist and even a slight perturbation creates a large charge response; 3) Higher κ in advanced technology node FinFET improves the electrostatics and boosts drive current by 13%, suggesting that this strategy is a promising approach to designing high-κ dielectrics for the next generation CMOS.

In this work we extend the compact Virtual Source (VS) model for nanoscale MOSFET from room temperature to 6K to advance the development of an ultra-compact model for low temperature CMOS (Cool-CMOS) technology. To achieve this we characterize 30 nm channel length bulk-Si CMOS FETs from 300K to 6K and extract the VS model parameters to investigate the ballistic efficiency of nanoscale FETs as a function of temperature. We conclude that while ballistic efficiency of nanoscale MOSFETs degrade in linear region as we approach cryogenic temperature, its ballistic efficiency improves in the saturation region at low temperature. Parametric V DD sweeps show that the VS model is also ready for use in low power cryogenic circuit design. Finally, the model is used to project performance of Cool CMOS technology for 15nm channel length FETs at deeply scaled nodes and prove its viability for use.

In this work, we present a comprehensive Kinetic Monte Carlo (KMC) modeling based statistical framework to evaluate the device-to-device variation of thin-film HfO 2 ferroelectric FET (FeFET). We conclude that the closing of the memory window in a FeFET array with device scaling can be attributed to: 1) limited number of domains; 2) variation among domains; 3) intrinsic stochasticity of individual domain switching. To enable further scaling of FeFET, co-optimization approaches from material, process, and device operation to control variation are proposed: i) increase the number of domains through material/process optimization (e.g. decrease of deposition temperature, etc.); ii) improve the uniformity of domains (e.g. minimizing the domain size variation and defect distribution, etc.); iii) increase the pulse amplitude/width to ensure deterministic switching of individual domains.

Hardware implementation of Quantum Processors require monolithic integration of CMOS controller and read-out interface circuits, operating at cryogenic temperatures (1-6K), to enable scale-up of the number of Q-bits and energy-efficient noise-tolerant circuit operation [1] (Fig. 1a). In this work, we investigate the critical role of interface traps near band-edge that affect both the sub-threshold swing (SS) and threshold voltage ( $(\mathrm{V}_{\mathrm{TH}})$ ) of high-K metal-gate (HKMG) n-channel MOSFETs at cryogenic temperature. We highlight two fundamental mechanisms that contribute to an increase in interface trap capacitance $(C_{\mathrm{it}})$ that affect both the SS and $(\mathrm{V}_{\mathrm{TH}})$ at cryogenic temperatures: (a) the proximity of the surface Fermi-level $(\mathrm{E}_{\mathrm{F}})$ to the edge of the conduction band $(\mathrm{E}_{\mathrm{C}})$ , where the density of interface traps $(D_{\mathrm{it}})$ is higher, and (b) higher sensitivity of the interface trap response for a given change in $\mathrm{E}_{\mathrm{F}}$ (Fig. 1b). We developed a physics-based cryo-CMOS transistor model [2], by incorporating multiple discrete interface traps located near $\mathrm{H}_{\mathrm{C}}$ and show excellent agreement with the experiments. This provides an important step towards optimization of future cryo-CMOS technology necessary for interface circuits in quantum processors.

We present a system implementing extremely energy-efficient inference on multi-channel biomedical-sensor data. We leverage Ferroelectric FET (FeFET) to perform classification directly on analog sensor signals. We demonstrate: (i) voltage-controlled multi-domain ferroelectric polarization switching to obtain 8 distinct transconductance $(\text{g}_{\text{m}})$ states in a 28nm HKMG FeFET technology [1], (ii) 30x tunable range in $\text{g}_{\text{m}}$ over the bandwidth of interest, (iii) successful implementation of artifact removal, feature extraction and classification for seizure detection from CHB-MIT EEG dataset with 98.46% accuracy and $ . false alarm rate for two patients, (iv) ultra-low energy of 47 fJ/MAC with 1,000x improvement in area compared to alternative mixed-signal MAC.

The paradigm of biologically-inspired computing endows the components of a neural network with dynamical functionality, such as self-oscillations, and harnesses emergent physical phenomena like synchronization, to learn and classify complex temporal patterns. In this work, we exploit the synchronization dynamics of a network of ultra-compact, low power Vanadium dioxide (VO 2 ) based insulator-to-metal phase-transition nano-oscillators (IMT-NO) to classify complex temporal pattern for speech discrimination. We successfully train a network of four capacitively coupled IMT-NOs to recognize spoken vowels by tuning their oscillation frequencies electrically according to a real-time learning rule and achieve high recognition rates of 90.5% for spoken vowels. Such an energy-efficient compact hardware with a small number of functional elements are a promising technology option for edge artificial intelligence.

Biologically plausible mechanism like homeostasis compliments Hebbian learning to allow unsupervised learning in spiking neural networks [1]. In this work, we propose a novel ferroelectric-based quasi-LIF neuron that induces intrinsic homeostasis. We experimentally characterize and perform phase-field simulations to delineate the non-trivial transient polarization relaxation mechanism associated with multi-domain interaction in poly-crystalline ferroelectric, such as Zr doped $\text{HfO}_{2}$ , that underlines the Q-LIF behavior. Network level simulations with the Q-LIF neuron model exhibits a 2.3x reduction in firing rate compared to traditional LIF neuron while maintaining iso-accuracy of 84-85% across varying network sizes. Such an energy-efficient hardware for spiking neuron can enable ultra-low power data processing in energy constrained environments suitable for edge-intelligence.

In this work, we exploit the spatio-temporal switching dynamics of ferroelectric polarization to realize an energy-efficient, and massively-parallel in-memory computational primitive for at-node sensor data fusion and analytics based on an industrial 28nm HKMG FeFET technology [1]. We demonstrate: (i) the spatio-temporal dynamics of polarization switching in HfO 2 -based ferroelectrics under the stimuli of sub-coercive voltage pulses using experiments and phase-field modeling; (ii) an inherent rectifying conductance accumulation characteristic in FeFET with a large dynamic range of $G_{\max}/G_{\min} > 100$ in the case of 3.0V, 50ns gate pulses; (iii) transition to more abrupt accumulation characteristics due to single/few domain polarization switching in scaled FeFET (34nm L G ); and (iv) successful detection of physiological anomalies from realworld multi-modal sensor data streams.

In spite of the rapid developments in various nanosensor technologies, it still remains challenging to realize a reliable ultrasensitive electrical biosensing platform which will be able to detect multiple viruses in blood simultaneously with a fairly high reproducibility without using secondary labels. In this paper, we have reported quantitative differentiation of Hep-B and Hep-C viruses in blood using nanoporous silicon oxide immunosensor array and artificial neural network (ANN). The peak frequency output (fp) from the steady state sensitivity characteristics and the first cut off frequency (fc) from the transient characteristics have been considered as inputs to the multilayer ANN. Implementation of several classifier blocks in the ANN architecture and coupling them with both the sensor chips, functionalized with Hep-B and Hep-C antibodies have enabled the quantification of the viruses with an accuracy of around 95% in the range of 0.04fM-1pM and with an accuracy of around 90% beyond 1pM and within 25nM in blood serum. This is the most sensitive report on multiple virus quantification using label free method.