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Reservoir computing (RC) possesses a simple architecture and high energy efficiency for time‐series data analysis through machine learning algorithms. To date, RC has evolved into several innovative variants. The next generation reservoir computing (NGRC) variant, founded on nonlinear vector autoregression (NVAR) distinguishes itself due to its fewer hyperparameters and independence from physical random connection matrices, while yielding comparable results. However, NGRC networks struggle with massive Kronecker product calculations and matrix‐vector multiplications within the read out layer, leading to substantial efficiency challenges for traditional von Neumann architectures. In this work, a hybrid digital‐analog hardware system tailored for NGRC is developed. The digital part is a Kronecker product calculation unit with data filtering, which realizes transformation of nonlinear vector of the input linear vector. For matrix‐vector multiplication, a computing‐in‐memory architecture based on resistive random access memory array offers an energy‐efficient hardware solution, which markedly reduces data transfer and greatly improve computational parallelism and energy efficiency. The predictive capabilities of this hybrid NGRC system are validated through the Lorenz63 model, achieving a normalized root mean square error (NRMSE) of 0.00098 and an energy efficiency of 19.42TOPS W−1.

Artificial intelligence for graph‐structured data has achieved remarkable success in applications such as recommendation systems, social networks, drug discovery, and circuit annotation. Graph convolutional networks (GCNs) are an effective way to learn representations of various graphs. The increasing size and complexity of graphs call for in‐memory computing (IMC) accelerators for GCN to alleviate massive data transmission between off‐chip memory and processing units. However, GCN implementation with IMC is challenging because of the large memory consumption, irregular memory access, and device nonidealities. Herein, a fully binarized GCN (BGCN) accelerator based on computational resistive random‐access memory (RRAM) through software–hardware codesign is presented. The essential operations including aggregation and combination in GCN are implemented on the RRAM crossbar arrays with cooperation between multiply‐and‐accumulation and content‐addressable memory operations. By leveraging the model quantization and IMC on the RRAM, the BGCN accelerator demonstrates less RRAM usage, high robustness to the device variations, high energy efficiency, and comparable classification accuracy compared to the current state‐of‐the‐art GCN accelerators on both graph classification task using the MUTAG and PTC datasets and node classification task using the Cora and CiteSeer datasets. These results provide a promising approach for edge intelligent systems to efficiently process graph‐structured data.

Abstract Time‐delayed reservoir computing with marked strengths of friendly hardware implementation and low training cost is regarded as a promising solution to realize time and energy‐efficient time series information processing and thus receives growing attention. However, achieving a sufficient number of reproducible reservoir states remains a significant challenge, which severely limits its computing performance. Here, an electric‐double‐layer‐coupled oxide‐based electrolyte‐gated transistor with a shared gate and varying channel lengths is developed to construct a deep time‐delayed reservoir computing system. A variety of short‐term synaptic responses related to inherent ion‐electron‐coupled dynamics at the electrolyte/channel interface are demonstrated, reflecting a flexibly regulable channel current. Different stable and tunable relaxation responses corresponding to varying channel lengths are obtained to enrich reservoir states combined with virtual nodes ways. The spoken‐digit classification and Hénon map prediction tasks are implemented with high accuracy (≈92.2%) and ultralow normalized root mean square error (≈0.013), respectively, validating the significant improvement of the computing performance by introducing additional relaxation responses. This work opens a promising pathway in exploiting oxide‐based electrolyte‐gated transistors for realizing temporal information processing hardware systems.

Abstract Neuromorphic computing aims to emulate the computing processes of the brain by replicating the functions of biological neural networks using electronic counterparts. One promising approach is dendritic computing, which takes inspiration from the multi-dendritic branch structure of neurons to enhance the processing capability of artificial neural networks. While there has been a recent surge of interest in implementing dendritic computing using emerging devices, achieving artificial dendrites with throughputs and energy efficiency comparable to those of the human brain has proven challenging. In this study, we report on the development of a compact and low-power neurotransistor based on a vertical dual-gate electrolyte-gated transistor (EGT) with short-term memory characteristics, a 30 nm channel length, a record-low read power of ~3.16 fW and a biology-comparable read energy of ~30 fJ. Leveraging this neurotransistor, we demonstrate dendrite integration as well as digital and analog dendritic computing for coincidence detection. We also showcase the potential of neurotransistors in realizing advanced brain-like functions by developing a hardware neural network and demonstrating bio-inspired sound localization. Our results suggest that the neurotransistor-based approach may pave the way for next-generation neuromorphic computing with energy efficiency on par with those of the brain.

Abstract Autonomous one‐shot on‐the‐fly learning copes with the high privacy, small dataset, and in‐stream data at the edge. Implementing such learning on digital hardware suffers from the well‐known von‐Neumann and scaling bottlenecks. The optical neural networks featuring large parallelism, low latency, and high efficiency offer a promising solution. However, ex‐situ training of conventional optical networks, where optical path configuration and deep learning model optimization are separated, incurs hardware, energy and time overheads, and defeats the advantages in edge learning. Here, we introduced a bio‐inspired material‐algorithm co‐design to construct a hydrogel‐based optical Willshaw model (HOWM), manifesting Hebbian‐rule‐based structural plasticity for simultaneous optical path configuration and deep learning model optimization thanks to the underlying opto‐chemical reactions. We first employed the HOWM as an all optical in‐sensor AI processor for one‐shot pattern classification, association and denoising. We then leveraged HOWM to function as a ternary content addressable memory (TCAM) of an optical memory augmented neural network (MANN) for one‐shot learning the Omniglot dataset. The HOWM empowered one‐shot on‐the‐fly edge learning leads to 1000× boost of energy efficiency and 10× boost of speed, which paves the way for the next‐generation autonomous, efficient, and affordable smart edge systems.

Abstract The hardware implementation of artificial neural networks requires synaptic devices with linear and high‐speed weight modulation. Memristors as a candidate suffer from excessive write variation and asymmetric resistance modulation that inherently rooted in their stochastic mechanisms. Thanks to a controllable ion intercalation/deintercalation mechanism, electrolyte‐gated transistors (EGTs) hold prominent switching linearity and low write variation, and thus have been the promising alternative for synaptic devices. However, the operation frequency of EGTs is seriously limited by the time that is required for the state stabilization, that is, the write‐read delay after each set/reset operation. Here, a Li‐ion‐based EGT (Li‐EGT) with write‐read delay of 3 ms along with multistates, low energy consumption, and quasi‐linear weight update is introduced. The origin of the short write‐read delay of the device is attributed to the permeable interface between electrolyte and gate electrode. Leveraging the Li‐EGT characteristic, near‐ideal accuracy (≈94%) on handwritten digital image data set has been achieved by the corresponding neural network simulation. These results provide an insight into the development of Li‐EGTs for high‐speed neuromorphic computing.

The unprecedented development of Internet of Things results in the explosion of spatiotemporal signals generated by smart edge devices, leading to a surge of interest in real‐time learning of such data. This imposes a big challenge to conventional digital hardware because of physically separated memory and processing units and the transistor scaling limit. Memristors are deemed a solution for efficient and portable deep learning. However, their ionic resistive switching incurs large programming stochasticity and energy, compromising their advantages in real‐time learning spatiotemporal signals. To address the aforementioned issues, we propose a novel hardware–software codesign. Hardware‐wise, the stochasticity in memristor programming is leveraged to produce random matrices for efficient in‐memory computing. Software‐wise, random convolutional‐pooling architectures are integrated with echo‐state networks that compute with the hardware random matrices and make real‐time learning affordable. The synergy of the hardware and software not only improves the performance over conventional echo‐state networks, that is, 90.94% and 91.67% (compared to baselines 88.33% and 62.50%), but also retains 187.79× and 93.66× improvement of energy efficiency compared to the digital alternatives on the representative Human Activity Recognition Using Smartphones (HAR) and CRICKET datasets, respectively. These advantages make random convolutional echo‐state network (RCESN) a promising solution for the future smart edge hardware.

Artificial neural networks have acquired remarkable achievements in the field of artificial intelligence. However, it suffers from catastrophic forgetting when dealing with continual learning problems, i.e., the loss of previously learned knowledge upon learning new information. Although several continual learning algorithms have been proposed, it remains a challenge to implement these algorithms efficiently on conventional digital systems due to the physical separation between memory and processing units. Herein, a software–hardware codesigned in‐memory computing paradigm is proposed, where a mixed‐precision continual learning (MPCL) model is deployed on a hybrid analogue–digital hardware system equipped with resistance random access memory chip. Software‐wise, the MPCL effectively alleviates catastrophic forgetting and circumvents the requirement for high‐precision weights. Hardware‐wise, the hybrid analogue–digital system takes advantage of the colocation of memory and processing units, greatly improving energy efficiency. By combining the MPCL with an in situ fine‐tuning method, high classification accuracies of 94.9% and 95.3% (software baseline 97.0% and 97.7%) on the 5‐split‐MNIST and 5‐split‐FashionMNIST are achieved, respectively. The proposed system reduces ≈200 times energy consumption of the multiply‐and‐accumulation operations during the inference phase compared to the conventional digital systems. This work paves the way for future autonomous systems at the edge.

The reservoir computing (RC) system, known for its ability to seamlessly integrate memory and computing functions, is considered as a promising solution to meet the high demands for time and energy-efficient computing in the current big data landscape, compared with traditional silicon-based computing systems that have a noticeable disadvantage of separate storage and computation. This review focuses on in-materio RC based on nanowire networks (NWs) from the perspective of materials, extending to reservoir devices and applications. The common methods used in preparing nanowires-based reservoirs, including the synthesis of nanowires and the construction of networks, are firstly systematically summarized. The physical principles of memristive and memcapacitive junctions are then explained. Afterwards, the dynamic characteristics of nanowires-based reservoirs and their computing capability, as well as the neuromorphic applications of NWs-based RC systems in recognition, classification, and forecasting tasks, are explicated in detail. Lastly, the current challenges and future opportunities facing NWs-based RC are highlighted, aiming to provide guidance for further research.

In embedded neuromorphic Internet of Things (IoT) systems, it is critical to improve the efficiency of neural network (NN) edge devices in inferring a pretrained NN. Meanwhile, in the paradigm of edge computing, device integration, data retention characteristics and power consumption are particularly important. In this paper, the self-selected device (SSD), which is the base cell for building the densest three-dimensional (3D) architecture, is used to store non-volatile weights in binary neural networks (BNN) for embedded NN applications. Considering that the prevailing issues in written data retention on the device can affect the energy efficiency of the system’s operation, the data loss mechanism of the self-selected cell is elucidated. On this basis, we introduce an optimized method to retain oxygen ions and prevent their diffusion toward the switching layer by introducing a titanium interfacial layer. By using this optimization, the recombination probability of Vo and oxygen ions is reduced, effectively improving the retention characteristics of the device. The optimization effect is verified using a simulation after mapping the BNN weights to the 3D VRRAM array constructed by the SSD before and after optimization. The simulation results showed that the long-term recognition accuracy (greater than 105 s) of the pre-trained BNN was improved by 24% and that the energy consumption of the system during training can be reduced 25,000-fold while ensuring the same accuracy. This work provides high storage density and a non-volatile solution to meet the low power consumption and miniaturization requirements of embedded neuromorphic applications.