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We investigated the effect of a sacrificial AlN layer on the deep energy level states of 4H-SiC surface. The samples with and without AlN layer have been annealed at 1300 °C for 30 minutes duration using a tube furnace. After annealing the samples, the changes of the carbon vacancy (VC) related Z1/2 defect characteristics were analyzed by deep level transient spectroscopy. The trap energy associated with double negative acceptor (VC(2-/0)) appears at ˜0.7 eV and was reduced from ˜0.687 to ˜0.582 eV in the sacrificial AlN layer samples. In addition, the capture cross section was significantly improved from ˜2.1×10-14 to ˜3.8×10−16 cm−2 and the trap concentration was reduced by approximately 40 times.

This paper presents an overall optimization procedure and the electrical performances of 1.2 kV/10 A 4H-SiC junction barrier Schottky (JBS) diodes with high current density. To achieve high current density, the epi-layer, the design parameters for active region including p-grid width and cell pitch, and the field limiting ring for edge termination were optimized with analytic calculation to estimate forward electrical performances and with Silvaco atlas™ simulator to estimate reverse electrical performances. Based on the systematic design, the JBS diodes were fabricated and electrically characterized. The experimental results showed that the breakdown voltage (BV) of JBS diode was significantly sensitive to field limiting ring (FLR) space and that the JBS diode with the ratio of pure Schottky contact area to total active area of 0.75 and the FLR space of 1.25 μm had optimum electrical performances such as a forward current density of 370 A/cm2, a reverse leakage current below 20 μA at the reverse anode voltage of 1.2 kV, and the BV of 1400 V. These were in coincidence with the simulation results within 10% error.

The use of SiO2/4H–SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) can be problematic due to high interface state density (Dit) and low field-effect mobility (μfe). Here, we present a tetra-ethyl-ortho-silicate (TEOS)-based low-pressure chemical vapor deposition (LPCVD) method for fabricating the gate oxide of 4H–SiC MOSFETs using nitric oxide post-deposition annealing. SiO2/4H–SiC MOS capacitors and MOSFETs were fabricated using conventional wet and TEOS oxides. The measured effective oxide charge density (Qeff) and Dit of the TEOS-based LPCVD SiO2/4H–SiC MOS capacitor with nitridation were 4.27 × 1011 cm−2 and 2.99 × 1011 cm−2eV−1, respectively. We propose that the oxide breakdown field and barrier height were dependent on the effective Qeff. The measured μfe values of the SiO2/4H–SiC MOSFETs with wet and TEOS oxides after nitridation were, respectively, 11.0 and 17.8 cm2/V due to the stable nitrided interface between SiO2 and 4H–SiC. The proposed gate stack is suitable for 4H–SiC power MOSFETs.

Nickel (Ni) is the most widely used metal for the formation of ohmic contact on n-type SiC. However, the irregular contact can potentially cause degradation in the device performance. To form the uniform ohmic interface, titanium (Ti) was applied as a barrier layer. Ni/Ti/SiC and Ti/Ni/SiC contact metal structures were prepared, and ohmic contacts were formed using a rapid thermal annealing process. The interfacial properties of both contact metal structures were enhanced by applying the Ti layer. The specific contact resistance of ohmic contacts showed a slightly lower or similar value (~ low 105 Ωcm2) compared with the specific contact resistance values formed from only the Ni contact metal.

We report a low knee voltage and high breakdown voltage 4H-SiC TSBS employing poly-Si/Ni dual Schottky contacts. A knee voltage was significantly improved from 0.75 to 0.48 V by utilizing an alternative low work-function material of poly-Si as an anode electrode. Also, reverse breakdown voltage was successfully improved from 901 to 1154 V due to a shrunk low-work-function Schottky region by a proposed self-align etching process between poly-Si and SiC. SiC TSBS with poly-Si/Ni dual Schottky scheme is a suitable structure for high-efficiency rectification and high-voltage blocking operation.

Five Σ-shaped dislocation arrays in 100-mm-diameter, 12-μm-thick 4H-SiC epitaxial wafers were observed using photoluminescence mapping. The structure of the Σ-shaped dislocation arrays was characterized using nondestructive analytical techniques of photoluminescence mapping, microphotoluminescence spectroscopy, and x-ray topography. Each Σ-shaped dislocation array consists of two basal plane dislocations (BPDs) at the interfacial dislocation terminal points and two half-loop arrays. The interfacial dislocation pairs nucleate from BPDs in the substrate. Three independent stresses lead to interfacial dislocations: thermal stress (τT), stress induced by misfit strain (τM), and interaction force (τI). The main cause of interfacial dislocation formation is attributed to the development of τT within the wafer due to temperature nonuniformity. τM and τI also contribute to the formation of interfacial dislocations. Larger stresses increase the BPD glide velocity in the interfacial dislocations, thereby producing longer Σ-shaped dislocation arrays.

In this paper, the effect of surface passivation on the breakdown voltage of 4H-SiC Schottky barrier diode (SBD) was investigated. The SBDs having various passivation structures were fabricated. The passivation layers consist of 2 different ones: (1) thermal oxide with a post oxidation annealing, or no oxide by removing the oxide, and (2) plasma-enhanced chemical vapor deposited (PECVD) oxide, phosphosilicate glass (PSG), or polyimide (PI). The results show that the SBD having a sacrificial oxide as 1st passivation layer and a PI as 2nd passivation layer exhibited lower leakage current by a factor of more than 2 for the reverse bias above 1000 V than the others and its breakdown voltage (VBR) was 2254 V, which corresponds to 93% VBR of a parallel-plane ideal device.

In this study, we fabricated and characterized graphene/molecule/graphene (GMG) vertical junctions with aryl alkane monolayers. The constituent molecules were chemically self-assembled via electrophilic diazonium reactions into a monolayer on the graphene bottom electrode, while the other end physically contacted the graphene top electrode. A full understanding of the transport properties of molecular junctions is a key step in the realization of molecular-scale electronic devices and requires detailed microscopic characterization of the junction’s active region. Using a multiprobe approach combining a variety of transport techniques, we elucidated the transport mechanisms and electronic structure of the GMG junctions, including temperature- and length-variable transport measurements, and transition voltage spectroscopy. These results provide criteria to establish a valid molecular junction and to determine the most probable transport characteristics of the GMG junctions.

A novel etching solution using molten potassium hydroxide (KOH) for the identification of dislocation types in a silicon-carbide (SiC) epilayer is identified. Threading screw dislocations (TSDs) and threading edge dislocations (TEDs) are rarely useful for size-based differentiation of etch pits in highly nitrogen (N)-doped SiC through conventional KOH etching. In this study, we report the role of sodium peroxide (Na2O2) and potassium dioxide (KO2) as oxidizing agent additives to the etchant for identifying the dislocation types in highly N-doped 4H-SiC. A Na2O2-KOH phase diagram was calculated to predict the chemical composition of the etchant. Solid-phase Na2O2 remained in the system when added to the etchant at concentrations greater than 13-wt% Na2O2, and it provided excess oxygen to the etchant. We experimentally confirmed that etch pit shapes became more hexagonal and that the etch pit sizes of TSDs and TEDs differed more greatly when more than 20-wt% Na2O2 was added to the etchant. We also found that the size distribution of TEDs was much smaller than that of TSDs after etching using Na2O2-KOH. Dissolved oxygen played an essential role in enhancing the anisotropic etching of highly N-doped SiC and allowed the dislocation types to be identified.

This paper presents the effects of thermal annealing performed at different temperatures on the forward current-voltage (I-V) characteristics to fabricate a 1.7-kV 4H-SiC Schottky barrier diode (SBD) with improved forward performances. To optimize the thermal annealing temperature, the SBDs were characterized by using precise low-current and high-current I-V measurements, a twodiode model analysis and grazing-incidence X-ray diffraction measurements. The results showed that a degradation in the ideality factor and a dramatic decrease in the turn-on resistance began at temperature above 550 °C. In particular, the turn-on resistance for the SBD annealed at 550 °C was reduced by 32% compared to that for the SBD without thermal annealing without any degradation in the Schottky barrier height. This was attributed to an expansion of Al crystallites caused by the thermal annealing.

We demonstrated 1.2-kV SiC trench metal–oxide semiconductor field-effect transistors with a double p-base structure via technology computer-aided design simulations (TCAD) and verified their breakdown characteristics by performing experiments. Two-different p-bases including a shallow junction and a deep junction were designed via Monte Carlo ion-implantation and two-dimensional device simulations with consideration of the punch-through behavior across the n-source/p-base/drift regions and the suppression of the electric-field crowding at the gate oxide near the bottom corner of the trench. Additionally, the trench depth and the distance between the edge of the deep p-base and the trench sidewall (DPG) were varied for a comparative analysis. When DPG was reduced, the breakdown voltage increased owing to the suppression of the electric field at the gate oxide, while the on-state drain current decreased owing to the increase in the JFET resistance.

SiC dry etching process for formation of a trenched-gate structure in trench metal-oxide-semiconductor field-effect-transistors employing bottom protection p-well (BPW) has been investigated. SF6/O2/Ar based inductively-coupled-plasma reactive-ion-etching were utilized with various variations in process parameters, such as bias power, ICP power, kind of gas species, working pressure and temperature. The effects of process parameters on trench profiles were analyzed by a cross-sectional scanning electron microscope and profilometer to suppress micro trenches at a bottom corner of the trench and improve SiC/SiO2 etch selectivity. We successfully demonstrated the micro-trench free SiC trench structure with high SiC/SiO2 etch selectivity of 3.7 at bias power of 1 kW, ICP power of 4 kW, SF6/O2/Ar flows of 6/6/8 sccm, working pressure of 15 mTorr and temperature of 20 °C.

Effects of junction profiles in bottom protection p-well (BPW) on electrical characteristics of 1.2 kV SiC trench-gate MOSFETs were investigated using simulation methods. Breakdown mechanisms of BPW in the device were also elucidated by energy-band diagram and electric-field distribution across trench-gate. Monte Carlo Al-implantation simulation on the trench structure for BPW formation was carried out with variations in peak depth (DBPW), concentration (NBPW), and thickness of SiO2 spacer (Tspacer) on trench sidewall. The SiC trench-gate MOSFETs with deep DBPW, high NBPW, and thin Tspacer are suitable for high drain voltage due to a shielded trench gate by BPW. However, specific on-resistance (Ron,sp) increased because of laterally penetrated Al into p-base and accumulation regions during ion implantation for BPW formation. In case of shallow DBPW, low NBPW, and thick Tspacer, however, the gate oxide at trench bottom corner is considerably vulnerable to the dielectric breakdown due to fully depleted BPW near trench bottom corner and electric-field crowding at gate oxide.

The influence of stacking faults (SFs) and triangular defects (TDs) on the electrical properties of 4H-SiC Schottky barrier diode (SBD) were investigated. The SF types and locations were distinguished and mapped by using room-temperature photoluminescence (PL) and optical microscope. SBDs were fabricated including the location of SF’s and TD’s. The effects of the types of defects and its area portion in the fabricated SBDs were also investigated. Based on the present data, 3C-TD has more harmful effect rather than the other SFs. The fabricated SBDs including SFs showed that increase of area portion of SF’s also resulted increase of specific on resistance of SBDs.

We investigated oxidized SiN gate oxides that have undergone post-oxidation annealing (POA) treatment using diluted O2 (10% O2 in N2) at 1100 °C. The oxidized SiN/SiC interfaces were characterized by using capacitance-voltage (C-V) measurements, Auger electron spectroscopy (AES), high-resolution transmission electron microscopy (HR-TEM), and X-ray photoelectron spectroscopy (XPS). POA for 60 min significantly improved the interface trap density (D it ), near-interface trap density (N it ), and effective oxide charge density (Q eff ) of the oxidized SiN. However, improvement was not observed for the as-oxidized SiN sample or the oxidized SiN sample that had undergone POA for 120 min. The electrical properties of metal-oxide semiconductor devices fabricated using these oxides are discussed in terms of the oxide chemical composition.

We report an investigation of the formation of triangular defects (TDs) in 4H–SiC expitaxial layers using Kelvin probe force microscopy (KPFM) and a nano-indenter. The results provide valuable information on the crystallographic structure, including the polytype nature of the TDs and surface potential profile. The TDs were also characterized using micro-Raman spectroscopy and high-resolution transmission electron microscopy. We found that the TDs were composed of a thick 3C-SiC band, as well as stacking faults (SFs) in the 4H-SiC epilayer.

The effect of sweeping direction on the capacitance–voltage (C–V) behavior of sputtered SiO2/4H-silicon carbide (SiC) metal-oxide semiconductor capacitors was investigated. Nitric oxide post-deposition annealing was conducted for the sputtered SiO2 on 4H-SiC. The sweeping direction of the measurement changed the C–V behavior and effective oxide charge density (Q eff) because of trapped electrons at the accumulation and detrapped electrons at the depletion. The nitrogen atoms near interface between SiO2 and 4H-SiC as a result of nitric oxide post-deposition annealing shifted the flat-band voltage in the negative direction. When the C–V was measured from depletion to accumulation, the absolute value of the Q eff after 60 min long annealing, 3.465 × 1010 cm−2 was less than that of the Q eff after 30 min long annealing, −2.912 × 1011 cm−2. The mechanisms of the nitric oxide post-deposition annealing on sputtered SiO2 on 4H-SiC are film densification and nitrogen passivation of the defects.

Purpose – The high density of defects mainly attributed to the presence of silicon oxycarbides, residual C clusters, Si- and C-dangling bonds at or near the SiO2/SiC interface degrades the performance of metal-oxide-semiconductor (MOS) devices. In the effort of further improving the quality and enhancement of the SiC oxides thickness, post-oxidation annealed by a combination of nitric acid (HNO3) and water (H2O) vapor technique on thermally grown wet-oxides is introduced in this work. The paper aims to discuss these issues. Design/methodology/approach – A new technique of post-oxidation annealing (POA) on wet-oxidized n-type 4H-SiC in a combination of HNO3 and H2O vapor at various heating temperatures (70°C, 90°C and 110°C) of HNO3 solution has been introduced in this work. Findings – It has been revealed that the samples annealed in HNO3 + H2O vapour ambient by various heating temperatures of HNO3 solution; particularly at 110°C is able to produce oxide with lower interface-state density and higher breakdown voltage as compared to wet-oxidized sample annealed in N2 ambient. The substrate properties upon oxide removal show surface roughness reduces as the heating temperature of HNO3 solution increases, which is mainly attributed due to the significant reduction of carbon content at the SiC/SiO2 interface by C=N passivation and CO or CO2 out-diffusion. Originality/value – Despite being as a strong oxidizing agent, vaporized HNO3 can also be utilized as nitridation and hydrogen passivation agent in high temperature thermal oxidation ambient and these advantages were demonstrated in 4H-SiC.

We fabricated 4H-SiC PiN diodes to analyze the correlation between the reverse characteristics, including current-voltage and failure characteristics, and defects. The leakage current and electroluminescense (EL) were measured at prebreakdown voltages. The diodes were etched by using molten KOH, and the locations of etch pits were compared with those of hot spots emitting during the EL measurements. The results showed that the reverse leakage current of a diode having defects in the p− junction termination extension (JTE) was at most 26 times higher than that of a diode having defects in an active area. The breakdown voltages of the diodes with threading screw dislocations (TSDs) and threading edge dislocations (TEDs) were reduced by 15.5% and 6.5%, compared with those of a diode without defects. In addition, the diodes were found to be destroyed due to weak edge termination resulting from misalignment and large pits.

The effects of hydrogen plasma treatment on surface morphologies and field emission performance of vertically aligned multi-walled carbon nanotubes were investigated. The hydrogen plasma treatment of vertically aligned multi-walled carbon nanotubes induces changing surface morphologies from flat surface to sharp conical shapes according to the plasma treatment time. The morphological changes owing to plasma treatment enhances field emission performance of vertically aligned carbon nanotubes so that the current density and field enhancement factor were considerably improved compared to those of as-grown one.

This paper introduces a phenomenon in which the leakage current of a 4H-SiC PiN diode was dramatically reduced without destruction during a bias stress. The reverse current-voltage characteristics of the 4H-SiC PiN diode were improved by using the bias-stress technique employing this phenomenon. Compared to a PiN diode bias-stressed for 10 s, a PiN diode bias-stressed for 600 s showed about a 2 order of magnitude lower leakage current and a 2.2 times higher breakdown voltage (1322 V for a PiN diode having an epi-layer thickness of 8 µm, which approaches 89% of the ideal value for a 1-dimensional (1-D) parallel plate structure).

Etch pits were investigated using the molten KOH selective etching method to examine dependence of etch pit shape and size on free electron concentration. The free electron concentrations of highly doped 4H-silicon carbide (SiC) were controlled by proton irradiation and thermal annealing, which was confirmed by a frequency shift in the LO-phonon–plasmon-coupled (LOPC) mode on micro-Raman spectroscopy. The proton irradiated sample with 5×10 15 cm −2 fluence and an intrinsic semi-insulating sample showed clearly classified etch pits but different ratios of threading screw dislocation (TSD) and threading edge dislocation (TED) sizes. Easily classified TEDs and TSDs on proton irradiated 4H-SiC were restored as highly doped 4H-SiC after thermal annealing due to the recovered carrier concentrations. The etched surface of proton irradiated 4H-SiC and boron implanted SiC showed different surface conditions after activation.

Micro-Raman spectroscopy is an excellent non-destructive analysis method, which compensates for disadvantages of KOH method. Raman shift of A1(LO) and E1(TO) band at threading screw dislocation(TSD) were investigated in n-type on/off-axis 4H- and 6H-SiC single crystal wafers by Micro-Raman scattering at room temperature. The results showed that A1(LO) band were shifted toward higher frequency while the E1(TO) band were shifted toward lower frequency on the on-axis wafers. The shifts are caused by increasing electron concentration and lattice disorder near the dislocation core, respectively. In the off-axis wafers, no shifts were observed possibly due to the measurement geometry which does not contain whole dislocation core.

We investigated the effect of the substrate temperature on the electrical and the optical properties of ZnO/4H-SiC structures. The n-type ZnO layer was grown on p-type 4H-SiC substrate by pulsed laser deposition to form p-n hetero-junction diode structure. The n-type ZnO thin films were deposited by pulsed laser deposition at different temperatures of 200, 400, and 600 °C, respectively. It was shown from transmission line method (TLM) and auger electron spectroscopy (AES) data that the sheet resistance of ZnO on SiC was increases from ~760 Ω/square to ~4000 Ω/square as the deposition temperature increases and the oxygen outdiffusion decreases. The I-V characteristics with and without illumination has also been studied.

The characteristics of Ga-doped zinc oxide (GaZnO) thin films deposited at different substrate temperatures (TS~250 to 550oC) on 4H-SiC have been investigated. Structural and electrical properties of GaZnO thin film on n-type 4H-SiC (100)were investigated by using x-ray diffraction, atomic force microscopy (AFM), Hall effect measurement, and Auger electron spectroscopy (AES). Hall mobility is found to increase as the substrate temperature increase from 250 to 550 oC, whereas the lowest resistivity (~3.3 x 10-4 Ωcm) and highest carrier concentration (~1.33x1021cm-3) values are observed for the GaZnO films deposited at 400 oC. It has been found that the c-axis oriented crystalline quality as well as the relative amount of activated Ga3+ Introduction ions may affect the electrical properties of GaZnO films on SiC.

We investigated the effect of the metal work-function and doping concentration on the barrier height of Ni-contacts with embedded nano-particles (NPs) on 4H-SiC surfaces. Both n-type epitaxial layers with ND=1×1016 cm-3, and layers doped by phosphorous implantation to a doping concentration of ~1×1019 cm-3 are used. The barrier height is reduced with increasing doping concentration and the silver (Ag) nano-particles (R~18.5 nm) further enhances the local electric field of the electrical contacts to 4H-SiC in comparison to gold (Au) nano-particles (R~20.2 nm). In the case of ion-implanted samples, the barrier height of the fabricated SiC diode structures with embedded Ag-NPs was significantly reduced by ~0.09 eV and ~0.25 eV compared to the samples with Au-NPs and the sample without NPs, respectively.

In this paper, we study the transient characteristics of 4H-SiC DMOSFETs with different interface charges to improve the turn-on rising time. A physics-based two-dimensional mixed device and circuit simulator was used to understand the relationship between the switching characteristics and the physical device structures. As the SiO2/SiC interface charge increases, the current density is reduced and the switching time is increased, which is due primarily to the lowered channel mobility. The result of the switching performance is shown as a function of the gate-to-source capacitance and the channel resistance. The results show that the switching performance of the 4H-SiC DMOSFET is sensitive to the channel resistance that is affected by the interface charge variations, which suggests that it is essential to reduce the interface charge densities in order to improve the switching speed in 4H-SiC DMOSFETs.

This letter presents a novel extraction method to accurately determine a reverse recovery time and a stored charge for ultrafast diodes. To obtain this, a test circuit to measure those parameters was accurately modeled by considering an inductance and a parasitic resistance, which are inherently embedded in the test circuit and lead to oscillation. The experimental results showed that the corrected reverse recovery time was reduced by 1.2 ns for an Si fast recovery diode, while by 6.8 ns for an SiC Schottky barrier diode, compared to their measured reverse recovery time.

Korea Electrotechnology Research Institute, Center for Energy Efficient Semiconductors, Changwon 641-120, Korea(Received August 5, 2011; Revised September 8, 2011; Accepted September 19, 2011)Abstract: The morphology of etch pits in commercial 4H-SiC epi-wafer were investigated by molten-KOH etching. The etching process was optimized in 525∼570℃ at 2∼10 min and the novel type of etch pits was revealed. This type of etch pits have been considered as TED (threading edge dislocation) II, its origin and nature, however, are not reported yet. In this work, the morphology and evolution of etch pits during epitaxial growth were analyzed and the different behavior between TED and TEDII was discussed.Keywords: 4H-SiC, Dislocation, KOH etching, Etch pit

Black SiC formation by plasma etching with SF6/O2 chemistry is reported. Black SiC was produced by depositing Si overlayer on SiC and then etching the Si/SiC stack sequentially, thus replicating the black Si morphology to SiC. Black SiC is obtained with almost zero reflectance over the wavelengths from 300 nm to 1050 nm. Thicker Si film was advantageous, and it was important to optimize the etch condition considering both the black Si morphology and the flattening effect of SiC.

ZrO2 thin film has been formed on n-type 4H-SiC substrate using a combination of metal sputtering (∼25 nm thick) and thermal oxidation (15 min at 500 °C) processes. Effects of post-oxidation annealing temperature (600–900 °C) on the physical and electrical properties of the thin film have been investigated. High resolution transmission electron microscopy attached with energy dispersive X-ray has been used to examine cross-sectional morphology and to study element chemical distribution of the investigated region. Selected area diffraction analysis has been employed to examine crystallinity of the samples. Metal-oxide-semiconductor capacitors have been fabricated to examine leakage current through the oxide using current–voltage measurement. Oxide-semiconductor interface-trap density has been extracted using capacitance–voltage measurement. The annealing process reduced leakage current density as low as one order of magnitude. However, breakdown voltage of the oxide has been reduced. Dielectric constant extracted from this work ranges from 22 to 80, depending on the annealing temperature.

4H-SiC nano-channel field effect transistors (FETs) with various widths of 3 μm-50 nm have been fabricated by "top-down" approach using electron-beam lithography process. It has been demonstrated that the gate controllability of the SiC FETs is improved with decreasing channel width. In the fabricated devices the threshold voltage V(th) for the 50 nm-width nano-channel FETs shows a positive shift (ΔV(th) = 1.4 V) with respect to that of the reference FETs. The on-current degradation of the SiC nano-channel FETs is found to be 1.5 times lower than that of the reference FETs at elevated temperatures up to 450 K. This attributed to the improved heat dissipation of the nano-channel structure with a large surface to volume ratio.

Current conduction mechanisms of atomic-layer deposited Al 2 O 3 (13 nm) stacked on different thermal nitrided SiO 2 thicknesses (2, 4, and 6 nm) on n-type 4 H-SiC have been systematically analyzed. It has been observed that the oxides were thermally stable at the investigated temperature range (25–140°C). By using different conduction process models, such as Schottky emission, direct tunneling, Fowler–Nordheim tunneling, Poole–Frenkel emission, and space-charge limited conduction, which consists of three limited conduction processes, namely, Ohm's law, Child's law, and trap-filled limit, the conduction mechanisms of charge through the oxides have been evaluated. It has been found that the conduction mechanisms were not affected by the investigated temperature range. A relationship plot has been proposed among nitrided SiO 2 thickness, electric field, and conduction mechanisms.

In this work, a study is presented of the static characteristics of 4H-SiC DMOSFETs obtained by adjustment of the p-base region. The structure of this MOSFET was designed by the use of a device simulator (ATLAS, Silvaco.). The static characteristics of SiC DMOSFETs such as the blocking voltages, threshold voltages, on-resistances, and figures of merit were obtained as a function of variations in p-base doping concentration from 1 × 10 17 cm to 5 × 10 cm and doping depth from 0.5 μm to 1.0 μm. It was found that the doping concentration and the depth of P-base region have a close relation with the blocking and threshold voltages. For that reason, silicon carbide DMOSFET structures with highly intensified blocking voltages with good figures of merit can be achieved by adjustment of the p-base depth and doping concentration.

Lateral double-implanted MOSFETs (LDIMOSFETs) fabricated on on-axis high-purity semi-insulating (HPSI) 4H-SiC substrates with gate field plates have been demonstrated for the enhancement of reverse blocking capability. The effects of gate field plate on LDIMOSFET were analyzed by simulation and experimental methods. The electric field concentration at the gate edge was successfully suppressed by a gate field plate. A high breakdown voltage of 934 V and a figure of merit of 14.6 MW/cm2 were achieved at L FP of 2 µm and L drift of 15 µm, while those of the conventional device without a gate field plate were 744 V and 13.3 MW/cm2, respectively. Also, the fabricated device shows stable blocking characteristics at a high temperature of 250 °C. The drain leakage was increased by only 22% at 250 °C compared with that at room temperature.

The effects of a trench profile and self-aligned ion implantation on the electrical characteristics of 1.2 kV 4H-SiC trench MOSFETs employing a bottom protection p-well (BPW) were investigated to improve blocking capability by simulation studies. The trench profile and thickness of a SiO2 spacer during self-aligned ion implantation for BPW affect electrons flow through a trench gate as well as E-field concentration at the gate insulator on a trench bottom. At trench angle higher than 84° and a SiO2 spacer thicker than 0.2 µm showed that the Al concentration penetrated into the trench sidewall during ion implantation is less than 0.3% in comparison with the background doping concentration in a drift region. Under the optimum conditions with a trench angle of 90° and 0.2-µm-thick SiO2 spacer, a high breakdown voltage of 1.45 kV with a low E-field peak in the gate insulator was achieved.

Silicon carbide is an attractive material for next-generation power devices, it has wide band gap and high thermal conductivity. SiC power devices can operate at higher temperatures and voltages compared to silicon devices. But, electrical characteristics of the SiC power devices can be deteriorated by SiC defects. The killer defects such as micropipes and stacking faults have been reduced through the development of SiC growth technique. But still the threading dislocations (TDs) and basal plane dislocations (BPDs) lowered the breakdown voltage and increased the leakage current during device operation [1]. In this study, we fabricated the 5 kV 4H-SiC Schottky barrier diode (SBD) to study the effect of SiC defect on electrical properties of SiC SBDs. The thickness of epitaxial layer was 50 um and the doping concentration is 1E15 cm-3. The device was fabricated with various length of junction termination extension (JTE). Ion implantation was performed to form p surge (Al, 500 °C, 5E19 cm-3) and JTE (B, 500 °C, 2E18 cm-3) regions. Activation annealing was performed at 1700 °C for 60 m. 100 and 30-nm-thick Ni were deposited as the cathode and front-side ohmic metal respectively, and then annealed at 950 °C for 90 s in RTA system. Finally, 100-nm-thick Ni was sputtered on front-side as a Schottky contact metal. We investigated the forward, reverse characteristics, and reverse breakdown voltage of the fabricated 4H-SiC SBDs. The diode characteristics, ideality factor (IF) and Schottky barrier height (SBH) were obtained from the forward electrical characteristics, about the 1.23 and 1.3 eV, respectively. The relative highly ideality factor may be due to rough surface of thick epitaxial layer. The breakdown voltage was obtained above 5 kV with JTE length longer than 60 um. During reverse characteristics the electrically weak points were observed using electroluminescence (EL). The EL spot was mainly aroused from electrically leaky points, it mostly observed at the edge of JTE. Some EL spots were observed inside the JTE or active region. The defects of the fabricated 4H-SiC 5 kV SBDs were analyzed using non-destructive analysis method, X-ray topography (XRT) and electron beam induced current (EBIC). We tried to determine the correlation between the electrical characteristics of the device and the crystal defects in the device. [1] H. Fujiwara, H. Naruoka, M. Konishi, K. Hamada, T. Katsuno, T. Ishikawa, Y. Watanabe, and T. Endo, Appl. Phys. Lett. 100, 242102 (2012). Figure 1

Metal-oxide–semiconductor characteristics of thermally grown nitrided SiO 2 (9–11.5 nm) on n-type 4H-SiC at 1175 °C in various N 2 O ambient (1, 10, and 50% N 2 O mixed with 99, 90, and 50% of high purity N 2 gas, respectively) have been investigated. The chemical composition of oxide–semiconductor interface has been evaluated by X-ray photoelectron spectroscopy. The interfacial layer consists of either silicon oxynitride, silicon nitride, and/or silicon oxide phases that may be segregated or mixed in a single layer. Depending on the percentage of N 2 O being used, the stoichiometry may vary accordingly. The lowest leakage current density is recorded for thin film oxide grown in10% N 2 O and it is limited to an applied electric field of not more than 7 MV/cm. This is attributed to the lowest density value of deep oxide trap in this sample if compared with others. The highest dielectric breakdown field has been obtained for thin film oxide grown in 50% N 2 O as this sample is having the lowest interface trap density and negative effective oxide charge. The origin of these charges is explained in the text.

We have investigated the electrical and physical properties of the oxidized-SiN with or without post oxidation annealing (POA) in N2 gas. A significant reduction in interface-trap density (Dit) has been observed in the oxidized-SiN with N2 POA for 60 min if compared with other oxides. The reason for this has been explained in this paper.

The 50W Quasi-resonant mode SMPS which adopted a normally-on-type SiC JFET as a switch has been designed and characterized. A simple decision circuit and an auxiliary power supply was utilized to safely protect the JFET from an in-rush current at initial operation stage and to provide sufficient negative voltage for a complete JFET drive. Even without a refine engineering, the SMPS showed 96% efficiency at a full load state.