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The European Spallation Source (ESS) accelerator is composed of superconducting elliptical cavities. When the facility is running, the cavities are fed with an electric field from klystrons. Parameters of this field are monitored and controlled by the low-level radio frequency (LLRF) system. Its main goal is to keep the amplitude and phase at a given set point. The LLRF system is also responsible for the reference clock distribution. During operation, the cavities are periodically experiencing strain caused by the Lorentz force, while the high gradient of the electric field is generated for the beam acceleration. Even small changes in the physical dimensions of a cavity shift its resonance frequency. This phenomenon, called detuning, causes significant power losses. It is actively compensated by the LLRF control system, which can physically tune lengths of the accelerating cavities with stepper motors (slow, coarse-grained control) and piezo elements (active compensation during operation). This article describes the implementation and tests of the software supporting various aspects of the LLRF system and cavities management. The Piezo Driver management and monitoring tool is dedicated to a piezo controller device. The LO distribution application is responsible for configuration of the local oscillator. The cavity simulator tool was designed to provide access to properties of the hardware device, emulating behavior of the elliptical cavities. IPMI Manager Software was implemented to monitor the state of MicroTCA.4 crates, which are a major part of the LLRF system architecture. All applications have been created using the experimental physics and industrial control system (EPICS) framework and built in the ESS EPICS Environment (E3).

International audience; The European Spallation Source (ESS), which is currently under construction, will be a neutron source based on 5 MW, 2 GeV superconducting proton linac. Among other beam instrumentation systems, this high intensity linac requires a Beam Loss Monitoring (BLM) system. An important function of the BLM system is to protect the linac from beam-induced damage by detecting unacceptably high beam loss and promptly inhibiting beam production. In addition to protection functionality, the system is expected to provide the means to monitor the beam losses during all modes of operation with the aim to avoid excessive machine activation. This paper focuses on the FPGA implementation of the real-time data processing in the nBLM system and presents preliminary result of a prototype system installed at LINAC4 at CERN.

The linear accelerators employed to drive Free Electron Lasers (FELs), such as the X-ray Free Electron Laser (XFEL) currently being built in Hamburg, require sophisticated control systems. The Low Level Radio Frequency (LLRF) control system should stabilize the phase and amplitude of the electromagnetic field in accelerating modules with tolerances below 0.02 % for amplitude and 0.01 degree for phase to produce ultra-stable electron beam that meets the conditions required for Self-Amplified Spontaneous Emission (SASE). The LLRF control system of 32-cavity accelerating module of the XFEL accelerator requires acquisition of more than 100 analogue signals sampled with frequency around 100 MHz. Data processing in real-time loop should complete within a few hundreds of nanoseconds. Moreover, the LLRF control system should be reliable, upgradable and serviceable. The Advanced Telecommunications Computing Architecture (ATCA) standard, developed for telecommunication applications, can fulfil all of the above mentioned requirements. The paper presents the architecture of a prototype LLRF control system developed for the XFEL accelerator. The control system composed of ATCA carrier boards with Rear Transition Modules (RTM) is able to supervise 32 cavities. The crucial submodules, like DAQ, Vector Modulator or Timing Module, are designed according to AMC specification. The paper discusses results of the LLRF control system tests that were performed at the FLASH accelerator (DESY, Hamburg) during machine studies.

Linear accelerators driving Free Electron Lasers (FELs), such as the Free Electron Laser in Hamburg (FLASH) or the X-ray Free Electron Laser (XFEL), require sophisticated Low Level Radio Frequency (LLRF) control systems. The controller of the LLRF system should stabilize the phase and amplitude of the field in accelerating modules below 0.02% of the amplitude and 0.01 degree for phase tolerances to produce an ultra stable electron beam that meets the required conditions for Self-Amplified Spontaneous Emission (SASE). Since the LLRF system for the XFEL must be in operation for the next 20 years, it should be reliable, reproducible and upgradeable. Having in mind all requirements of the LLRF control system, the Advanced Telecommunications Computing Architecture (ATCA) has been chosen to build a prototype of the LLRF system for the FLASH accelerator that is able to supervise 32 cavities of one RF station. The LLRF controller takes advantage of features offered by the ATCA standard. The LLRF system consists of a few ATCA carrier blades, Rear Transition Modules (RTM) and several Advanced Mezzanine Cards (AMCs) that provide all necessary digital and analog hardware components. The distributed hardware of the LLRF system requires a number of communication links that should provide different latencies, bandwidths and protocols. The paper presents the general view of the ATC A-based LLRF system, discusses requirements and proposes an application for various interfaces and protocols in the distributed LLRF control system.

The subject of this paper is the design and construction of a new generation of superconducting cavity accelerator measurement and control system. The old system is based on a single digital signal processor (DSP). The new system uses a large programmable array circuit (FPGA) instead, with a multi-gigabit optical link. Both systems now work in parallel in the Free Electron Laser in Hamburg (FLASH). The differences between the systems are shown, based on the measurement results of the working machine. The major advantage of the new system is a bigger area of stability of the machine control loop.

The measurements of superconducting cavity parameters before module assembly stage are very important, because they allow to evaluate critical properties (resonant frequency, quality factor of accelerating mods) of individual resonating cavities. Such measurements are performed in Vertical Test Stand facilities. One of such setups is Vertical Test Stand II (VTS II) at DESY. It is used for conditioning and characterization of cavities for FEL (Free Electron Laser) experiments (especially for FLASH and European XFEL). In the previous set-up cavities in VTS II were operated in Continuous Wave mode using analog control system. The core of the system was analog Phase Lock Loop used to lock phases of incident wave and transmitted wave. All measurements were done using external equipment such as oscilloscopes, spectrum network analyzers, etc. The main disadvantage of such system was lack of flexibility - each small modification required precise system tuning, no new functionality could be added and automation of measurements was hard to achieve. The paper presents new solution of the control system for VTS II based on digital hardware. It allows to overcome most of disadvantages of previous analog system. All measurements and control functions are integrated on a single (FPGA based) computation board, which is fully integrated with external control system. The usage of such system offers functionality such as long term data acquisition (due to Continuous Wave operation of the cavity), special modes of operation (like Self Excited Loop or Digital PLL - due to low bandwidth of measured resonator) and possibility of measurement process automation. Additionally developed user interfaces allow remote access to the system parameters and flexible configuration. The paper discusses each sub-system, presents measurement results and overall system performance evaluation together with some views for future functionality development.

The paper describes development of a new version of photonic and electronic control and measurement system for FLASH Laser under development in DESY Hamburg accelerator laboratory. The system is called SIMCON 3.1. and is a developmental continuation of previous systems SIMCON 1.0, SIMCON 2.1 and SIMCON 3.0. It differs from the previous systems by considerably bigger resources: 10 fast analog input channels, bigger FPGA chip with two power PC - CPU units, two multi-gigabit optical links, GbE interface, booting possibility from flash memory card. The PCB is done in VME mechanical and electrical standard. It is designed for usage in tests for FLASH Laser development.

The paper presents an idea, design and realization of a gigabit, optoelectronic synchronous massive data concentrator for the LLRF control system for FLASH and XFEL superconducting accelerators and lasers. The design bases on a central, large, programmable FPGA VirtexIIPro circuit by Xilinx and on eight commercial optoelectronic transceivers. There were implemented peripheral devices for embedded PowerPC block like: memory and Ethernet. The SIMCON 4.0 module was realized as a single, standard EURO-6HE board with VXI/VME-bus. Hardware implementation was described for the most important functional blocks. Construction solutions were presented.

FPGA devices are often used in High Energy Physics and accelerator technology experiments, where the highest technologies are needed. To make FPGA based systems more flexible, common technique is to provide SoC (System on a Chip) solution in the FPGA, which is in most cases a CPU unit. Such a combination gives possibility to balance between hardware and software implementation of particular task. SoC solution on FPGA can be very flexible, because in simplest cases no additional hardware is needed to run programs on CPU, and when system has such devices like UART, SDRAM memory, mass storage and network interface, it can handle full featured operating system such as Linux or VxWorks. Embedded process can be set up in different configurations, depending on the available resources on board, so every user can adjust system to his own needs. Embedded systems can be also used to perform partial self-reconfiguration of FPGA logic of the chip, on which the system is running. This paper will also present some results on SoC implementations in a Low Level RF system under design for the VUV Free Electron Laser, FLASH, DESY, Hamburg.

It may be predicted now, even assuming a very conservative approach, that the next generation of the Low Level RF control systems for future accelerators will use extensively such technologies like: very fast programmable circuits equipped with DSP, embedded PC and optical communication I/O functionalities, as well as multi-gigabit optical transmission of measurement data and control signals.

The paper describes design, construction and initial measurements of an eight channel electronic LLRF device predicted for building of the control system for the W-FEL accelerator at DESY (Hamburg). The device, referred in the paper to as the SIMCON 3.0 (from the SC cavity simulator and controller) consists of a 16 layer, VME size, PCB, a large FPGA chip (VirtexII-4000 by Xilinx), eight fast ADCs and four DACs (by Analog Devices). To our knowledge, the proposed device is the first of this kind for the accelerator technology in which there was achieved (the FPGA based) DSP latency below 200 ns. With the optimized data transmission system, the overall LLRF system latency can be as low as 500 ns. The SIMCON 3.0 sub-system was applied for initial tests with the ACCl module of the VUV FEL accelerator (eight channels) and with the CHECHIA test stand (single channel), both at the DESY. The promising results with the SIMCON 3.0. encouraged us to enter the design of SIMCON 3.1. possessing 10 measurement and control channels and some additional features to be reported in the next technical note. SIMCON 3.0. is a modular solution, while SIMCON 3.1. will be an integrated board of the all-in-one type. Two design approaches - modular and all-in-one - after branching off in this version of the Simcon, will be continued.© (2006) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Today, the fast optical data transmission is one of the fundamentals of modern distributed control systems. The fibers are widely use as multi-gigabit data stream medium. For a short range transmission, the multimode fibers are in common use. The data rate for this kind of transmission exceeds 10 Gbps for 10 Gigabit Ethernet and 10G Fibre Channel protocols. The Field Programmable Gate Arrays are one of the opportunities of managing the optical transmission. This article is concerning a synchronous optical transmission system via a multimode fiber. The transmission is controlled by the FPGA of two manufacturers: Xilinx and Altera. This paper contains the newest technology overview and market device parameters. It also describes a board for the optical transmission, technical details of the transmission and optical transmission results.

The paper describes design, construction and initial measurements of an eight channel electronic LLRF device predicted for building of the control system for the VUV-FEL accelerator at DESY (Hamburg). The device, referred in the paper to as the SIMCON 3.0 (from the SC cavity simulator and controller) consists of a 16 layers, VME size, PCB, a large FPGA chip (VirtexII-4000 by Xilinx), eight fast ADCs and four DACs (by Analog Devices). To our knowledge, the proposed device is the first of this kind for the accelerator technology in which there was achieved (the FPGA based) DSP latency below 200 ns. With the optimized data transmission system, the overall LLRF system latency can be as low as 500 ns. The SIMCON 3.0 sub-system was applied for initial tests with the ACC1 module of the VUV FEL accelerator (eight channels) and with the CHECHIA test stand (single channel), both at the DESY. The promising results with the SIMCON 3.0 encouraged us to enter the design of SIMCON 3.1 possessing 10 measurement and control channels and some additional features to be reported in the next technical note. SIMCON 3.0 is a modular solution, while SIMCON 3.1 will be an integrated board of the all-in-one type. Two design approaches - modular and all-in-one, after branching off in this version of the SIMCON, will be continued.

A new version of the SIMCON system is presented in this paper. The SIMCON stands for the microwave, resonant, superconductive accelerator cavity simulator and controller (embracing the hardware and software layers). The current version of the SIMCON is 3.1. which is a considerable step forward from the previous 8-channel version 3.0. which was released at the beginning of 2005 and was made operable in April. Many important upgrades were implemented in SIMCON 3.1. It is a stand-alone VME board (whereas SIMCON 3.0 was modular) based on the Virtex II Pro 30 chip with two embedded Power PCs and DSP blocks. It has Ethernet and multiple gigabit optical I/Os. The Simcon 3.1 board provides 10 ADC channels. The architecture idea and block diagrams of the PCB for SIMCON 3.1. are presented. Some of the applied novel technical solutions, Protel® views and schemes are shown. A number of initial conclusions were drawn from a few month experience with the development of this new board. The tables of predicted system parameters are quoted.

The work presents a structural and functional model of a distributed low level radio frequency (LLRF) control system for the TESLA-XFEL accelerator. The design of a system basing on the FPGA chips and multi-gigabit optical network was debated. The system design approach was fully parametric. The major emphasis is put on the methods of the functional and hardware concentration to use fully both: a very big transmission capacity of the optical fiber telemetric channels and very big processing power of the latest series of the, DSP enhanced and optical I/O equipped, FPGA chips. The subject of the work is the design of a universal, laboratory module of the LLRF sub-system. Initial parameters of the system model under the design are presented.