Search

Copper-manganese (Cu-Mn) alloys are usually used in resistance materials with a low resistance and low temperature coefficient of resistance (TCR). However, current research and development has been mainly focused on thin film materials deposited by the sputtering method, which is also by the cost due to its vacuum equipment. In the study, three kinds of electrochemical deposition methods were used to prepare a Cu-Mn-Cu switch structure. Firstly, we prepared the Al thick film as the sacrificial layer by screen printing on the Al2O3 substrate, and then transformed the Al thick film into the Cu thick film by the chemical oxidation-reduction replacement reaction at 80°C for 75 minutes. Secondly, the electroplating method was used to deposit Mn on the as-replaced Cu film. Based on the results of the SEM and XRD, it could be seen that a high quality and desired Cu-Mn 9:1 ratio could be obtained by depositing at 1.6V for 10 minutes. Finally, the top Cu layer was coated on the surface again by electroless plating to complete the sandwich structure of the Cu-Mn-Cu. Sequentially, annealing under normal pressure in reducing the atmosphere was done to make the Cu and Mn interdiffusion into the alloy phase. Both the XPS and Raman confirmed that annealing in a nitrogen-hydrogen atmosphere could extremely reduce the possibility of manganese oxidation and showed promising electrical properties such as a low temperature coefficient of resistance at 900℃ (150 ppm).

A molding coil is prepared by filling and dry pressing granulated alloy magnetic powders directly onto enameled wire. As the molding coil is developed toward miniaturization, the granules consisting of magnetic powder and organic binder cannot uniformly fill the small space in the coil center column during molding. This leads to a porous microstructure or cracks. The uneven packing problem in the coil center column was effectively solved in this study by applying a screen printing process using high-solid-content magnetic pastes. Bisphenol A epoxy resin has the benefits of excellent mechanical, bonding, electrical, corrosion resistance, low shrinkage and low cost properties. However, the viscosity is too high for use as a binder for high-solid-content magnetic paste. The magnetic paste viscosity can be reduced by substituting some low viscosity reactive diluent (butyl glycidyl ether) for Bisphenol A epoxy resin. It was observed that the relative density and magnetic properties (such as initial permeability, saturation magnetization, and core loss) can be effectively improved by increasing the monomer addition because the monomer acts as a lubricant that helps the magnetic particles rearrange during compaction. However, as monomer addition becomes greater than half the epoxy resin weight percent, the sample bending strength decreases.

A molded-type coil is prepared by filling and dry pressing granulated alloy magnetic powders directly onto enameled wire. As the molded-type coil is developed toward miniaturization, the granules consisting of magnetic powder and organic binder cannot uniformly fill the small space in the coil center column during molding. This leads to a porous microstructure or cracks. In this study, magnetic alloy powder coils were prepared using a screen-printing process using high-solid-content magnetic pastes. The magnetic powder was surface-modified with titanate coupling agent to improve the magnetic powder and epoxy resin compatibility, thereby improving magnetic powder mixing with epoxy resin and reducing the high solid content magnetic paste viscosity. The experimental results showed that the relative density and magnetic properties (such initial permeability, core loss, and coercivity) can be significantly enhanced using titanate coupling agent surface modification.

Monolithic 3D-IC is one of the solutions to relieve Moore’s law with vertically integrating circuits for sub-1nm technology nodes. Therefore, thin-film transistors (TFTs) play an important role in this trend because of their low fabrication temperature to realize back-end circuits. On the other hand, 3D integrating filter, duplexer, switch, and so on is necessary as antennas array requirements increase in 5G or beyond. Consequently, it is foreseeable to adopt TFTs to implement radio frequency (RF) devices. Fig. 1 shows the schematic ideal 3D SoC for sub-1nm technology. Our previous research tried to demonstrate high-frequency back-end devices based on the gate-all-around stacked nanosheet low-temperature polycrystalline silicon channel (GAA NS LTPS). Fig.2 shows the current-voltage transfer characteristics of different width designs of LTPS and α-IGZO devices. The only way to enhance GAA NS LTPS RF devices with the same process is by increasing channels. However, it leads to a larger footprint, and the frequency doesn’t boost with increasing channels in proportion because of the capacitance between the multiple channels. In the meantime, the LTPS gate controllability becomes poor, and threshold voltage shifts significantly when the drive current is improved by widening channel width. Consequently, a-IGZO is adopted as the channel material of RF devices to solve the problem mentioned above. The a-IGZO film is back-end compatible and has transparency and high uniformity. The most important is that the gate controllability decay phenomenon is negligible no matter what the channel width is, which is helpful for different width designs. In contrast, IGZO devices can keep their threshold voltage and have ultra-low leakage current due to a large bandgap. According to the system on panel (SoP) trend, we attempt to integrate RFIC with the peripheral circuit on a substrate. Therefore, a-IGZO is also introduced as a pull-down transistor in a CMOS for power reduction and process simplicity. To further minimize the footprint, the a-IGZO devices are nanoscale and stacked on the p-type LTPS as the defined heterogeneous CFET (HCFET), which is demonstrated in the previous study [1]. In this talk, we will discuss HCFET architecture in detail. We compared junctionless mode (JL) and inversion mode (IM) for bottom p-type LTPS in HCFET. In our results, IM is better than JL as the junction structure for bottom PMOS because the requirement of the bottom channel in a HCFET is thin and width flexible for design. In addition, a trench gate of the bottom device plays an important role in HCFET. The trench tri-gate structure can avoid gate dielectric damage by plasma in the etching process, keep the top IGZO layer continuously and enhance performance compared to the general tri-gate structure. On the other hand, the gate of top n-type IGZO can be bottom gate only or dual gate for different requirements. Finally, HCFET can significantly reduce the distance between IGZO and p-type LTPS channels to save power and lower latency in the circuit. [1] S. -W. Chang et al., "First Demonstration of Heterogeneous IGZO/Si CFET Monolithic 3-D Integration With Dual Work Function Gate for Ultralow-Power SRAM and RF Applications," in IEEE Transactions on Electron Devices, vol. 69, no. 4, pp. 2101-2107, April 2022, doi: 10.1109/TED.2021.3138947. Figure 1

In this study, a pretreatment on aluminum oxide substrate by sputtering with an aluminum oxide film is investigated to improve the surface roughness of a deposited NiCrSi (55/40/5) thin film resistor. Effect of sputtering parameters and thermal treatment on the deposited aluminum oxide film on aluminum oxide substrate are studied. Aluminum oxide thin film with Ar/O2 flow rate of (55/5) sccm shows the lowest surface energy at 41.5 J/m2 that would be helpful in improving the quality of the deposited resistive NiCrSi thin film. On the other hand, with increasing the thickness of aluminum oxide film, the surface roughness of the alumina substrate is observed to be significantly decreased and is quite helpful in improving the continuity of deposited resistive NiCrSi film. According to our investigations, developing a narrow distribution of high resistance thin film resistor by reducing the thickness of NiCrSi film is feasible when the aluminum oxide substrate was pretreated by sputtering aluminum oxide film and the continuity of NiCrSi thin film can be significantly improved, leading to a narrow resistance distribution of thin film resistor.

This study proposes a logic non-volatile memory (NVM) device based on the state-of-the-art gate-all-around (GAA) nanosheet process. By adopting a complementary FET structure, we not only reduce the layout footprint area but also demonstrate the compatibility with sub-3nm nanosheet CMOS technology. We simulated the device in TCAD for program and erase operations, considering both Fowler Nordheim tunneling and hot carrier injection mechanisms. The memory window is optimized by adjusting the device structure, such as tunneling and blocking oxide thicknesses, top- and bottom-channel width, and the floating gate length, resulting in a significant enhancement in the memory window. Finally, NAND/NOR type CFET logic NVM are demonstrated to reveal the possible applications of gate-all-around stacked junctionless nanosheet transistor towards embedded flash.

With the development of thick-film paste, silver and copper are circulating in the market as the electric conductive fillings currently. Unfortunately, the cost of silver is exceedingly high, while the copper has to be sintered in the reducing atmosphere. In this study, we proposed to exert aluminum as the filling due to its low cost, good electrical conductivity, and capability of being sintered in air. By means of the fracture mechanism of the oxidation layer of the Al surface and the liquid phase sintering, the Al paste with high solid content is used to implement high electrical conductivity. Based on that Al powder with large particle size tends to fracture easily, while it is easy for Al powder with small size to fill the gap, we mixed Al powder with large and small particle sizes at different proportion, so that the internal micro-structure and the oxidization are observed. However, when glass frit was added into mixed Al powder, the Al particles are wet by glass frit for bonding Al particles as well as inhibiting oxidation. Effect of the glass frit content and the solid content of Al paste on conductivity are investigated in this study. The sheet resistance of Al paste sintered at 850 °C for 10 min. can be reduced to 4.5 mΩ/□ when Al paste is formulated based on the mixed Al particles with proportion of big to small (4:1) at 10 wt% glass frit content and 80 wt% solid content.

In this study, we evaluate the defects and charges caused by the ultraviolet (UV)/vacuum ultraviolet (VUV) irradiation in the high-k/metal gate stack structure, especially in HfO2 layer and at Si/HfO2 interface. First, we measured the photons irradiating to the surface in the neutral beam etching (NBE) system and in the conventional inductively coupled plasma (ICP) system through optical emission spectroscopy (OES), respectively. By using this method, we evaluate the ability of reducing UV/VUV irradiation damage in the NBE system. As a result, photon intensity detected in the ICP system shows larger magnitude as compared to the NBE system, which indicates the UV/VUV irradiation is more severe in the ICP system. Moreover, in order to understand the twisting of electrical characteristics caused by UV/VUV irradiation, we set the prefabricated metal-oxide-semiconductor (MOS) capacitors in both systems to absorb the irradiation of UV/VUV photons respectively. The electrical characteristics of the etched MOS capacitors and its related plasma-induced damage model are discussed. The result of the devices exposed in the ICP system reveals a greater electrical characteristics shift compared to the devices in NBE such as the interface trap density (Dit) in case of NBE is 3.55621×1012 cm-2eV-1 and in case of ICP is higher i.e., 4.19961×1012 cm-2eV-1.

In this study, amorphous FeSiCrB alloy powder, carbonyl iron powder, and high-temperature heat-resistant silicone resin were used to prepare power molding inductors, and the effects of different heat treatment procedures on the magnetic properties were investigated. Two heat treatment procedures were used. Procedure 1: Amorphous FeSiCrB alloy powder was pre-heat-treated, then mixed with carbonyl iron powder and silicone resin and uniaxially pressed to prepare power inductors. Procedure 2: A mixture of amorphous FeSiCrB alloy powder, carbonyl iron powder, and silicone resin was uniaxially pressed. After dry pressing, the compacted body was heat-treated at 500 °C. Heat treatment after compaction can reduce the internal strain caused by high-pressure compaction and promote the crystallization of superparamagnetic nano-grains simultaneously. Therefore, the compacted sample after heat treatment exhibited better magnetic properties.

In this work, a high-pressure annealing (HPA) technique at 6 atm over a wide range of temperatures (200 °C–450 °C) was used for post-metallization annealing on a high-k/metal gate MOS capacitor. To verify the ability of HPA to improve interface trap density and leakage issues another MOS capacitor with the same structure was annealed by microwave annealing (MWA) for comparison. The electrical performance of the capacitors under different annealing conditions were analyzed and the difference in characteristics such as flat-band voltage shift, oxide trapped charge, interface state density and leakage current were compared. HPA demonstrates a low trap density when compared with other annealing techniques, indicating potential removal of charge traps and a reduction in leakage current density. The results show that HPA is more effective at minimizing the oxide trapped charged at low temperature than MWA at 3000 W and the reduction in leakage current density after HPA at low temperatures corresponds to the reduction in charge traps. HPA at low temperature demonstrates great potential as a post-metallization annealing process for high-k/metal gate structures due to its ability to overcome undesired effects such as diffusion of Al into the dielectric layer.

In this study, we fabricate Si/SiGe core-shell Junctionless accumulation mode (JAM)FinFET devices through a rapid and novel process with four main steps, i.e. e-beam lithography definition, sputter deposition, alloy combination annealing, and chemical solution etching. The height of Si core is 30 nm and the thickness of Si/SiGe core-shell is about 2 nm. After finishing the fabrication of devices, we widely studied the electrical characteristics of poly Si/SiGe core-shell JAM FinFET transistors from a view of different Lg and Wch. A poly-Si/SiGe core -shell JAMFETs was successfully demonstrated and it also exhibits a superior subthreshold swing of 81mV/dec and high on/off ratio > 105 when annealing for 1hr at 600°C. The thermal diffusion process condition for this study are 1hr at 600°C and 6hr at 700°C for comparison. The annealing condition at 700oC for 6 hours shows undesired electrical characteristics against the other. Results suggests that from over thermal budget causes a plenty of Ge to precipitate against to form SiGe thin film. Annealing JAMFETs at low temperature shows outstanding Subthreshold swing and better swing condition when compared to its counterpart i.e. at higher temperature. This new process can still fabricate a comparable performance to classical planar FinFET in driving current.

A planar inductor with excellent magnetic characteristics was successfully prepared by screen printing high solid content iron-based alloy magnetic pastes onto copper-clad laminates (CCL). The sample was then cold-isostatic pressed (CIP) to increase the packing density. To solve the problems of low electrical resistivity and low power handling capability of alloy powders for power inductor applications, an epoxy resin vehicle was added to form an insulating layer on top of the iron-based alloy powder surfaces and distribution gaps between the alloy powders. A central column was formed by punching in the center of the planar inductor and filled with magnetic paste to increase the inductance, magnetic flux channeling, and storage energy. A planar inductor 8.5 mm×7.0 mm×0.4 mm in size with an inductance value of about 2.7μH at 1 MHz, a quality factor of 10 to 13, and inductance decline rate of about 5% at a DC bias of 2.5 A can be successfully prepared using the proposed method. A 3D electromagnetic field finite element analysis tool (ANSYS Maxwell R19.3) was used to simulate the coil geometry and magnetic paste formulation effects on the magnetic flux density distribution, and the planar inductor electromagnetic properties to identify the optimal parameters. The differences between the simulation and the experimental planar inductor DC-bias superposition characteristics were compared. The deviations between the measured and simulated results are only within 6%, suggesting that the simulation has very high accuracy and reliability.

With the increase in the aspect ratio of the interconnect features in integrated circuits, the direct electroplating of Cu on diffusion barrier without sputtered Cu seed layers is attracting more and more attention. In this study, direct electroplating of Cu onto sputtered CoW films with various W concentration in acidic CuSO4 solution is investigated. Also, the adhesion and anti-diffusion properties of the CoW thin films for Cu are explored. The results show that Cu films cannot be electrodeposited on thin Co layers due to corrosion of Co in the acidic bath. For CoW alloys, higher W concentration is found to be beneficial for suppressing corrosion of CoW films and also improving the thermal stability. However, on the surface of Cu/CoW films with high W concentration, Cu agglomeration and pin-holes were found after annealing, indicating poor adhesion between Cu and high-W-content CoW alloys. In this study, CoW alloys with moderate W concentration around 50% are found to be a direct platable material which also demonstrates desirable adhesion and anti-diffusion characteristics for Cu interconnects application. Display Omitted Addition of W over 50% in CoW alloys can suppress corrosion of Co in acidic bath.Wetting ability of CoW alloys degrades with increasing W content.Higher W concentration in CoW alloys leads to superior anti-diffusion ability against Cu.CoW with 50% W content can serve as seedless barriers for Cu interconnects.

Dielectric breakdown induced by Cu ion migration in porous low-k dielectric films has been investigated in alternating-polarity bias conditions using a metal–insulator–metal capacitor with Cu top metal electrode. The experimental results indicated that Cu ions migrated into the dielectric film under stress with positive polarity, leading to weaker dielectric strength and shorter time to failure (TTF). In the alternating-polarity test, the measured TTFs increased with decreasing stressing frequency, implying backward migration of Cu ions during reverse-bias stress. Additionally, compared with a direct-current stress condition, the measured TTFs were higher as the frequency was decreased to 10−2 Hz. The electric-field acceleration factor for porous low-k dielectric film breakdown in the alternating-polarity test was also found to increase. This Cu backward migration effect is effective when the stressing time under negative polarity is longer than 0.1 s.

As-deposited CuInSe₂ thin films by electrodeposition method are usually accompanied with amorphous structure which is regarded detrimental for solar cell conversion efficiency. In this work, we proposed an annealing method under high pressure for improving the conversion efficiency of electrodeposited CuInSe₂ thin film solar cells, and the microstructure of high-pressure annealed CuInSe₂ films were also investigated. The annealing pressure was set from 100 kPa to 250 kPa, and the annealed CuInSe₂ thin films were then fabricated into solar cell using standard process. Field-emission scanning electron microscopy (FESEM) images show that CuInSe₂ films with higher annealing pressure demonstrate denser and smoother surface morphology. Results from X-ray diffraction (XRD) and Raman spectra indicate that annealing under high pressure enhanced the (1 1 2) preferential orientation of CuInSe₂ films and also eliminated binary Cu–Se phases. Finally, through annealing CuInSe₂ absorber layer under 200 kPa, the fill factor of the CuInSe₂ solar cell was found to be improved from 28.4% to 55% and the efficiency from 2.77% to 6.91%.

In this paper, FinFETs are realized by integrating neutral beam etching(NBE) and microwave annealing (MWA) into the fabrication process. Electrical characteristics are measured at room temperature and parameters such as Sub-threshold swing of 89 mV/decade, Ion/Ioff of 106, DIBL of 72 mV/V and effective mobility (μeff) of 502 cm2V−1 s−1 are obtained with Wfin/Lgate = 40/100 nm. These characteristics are superior by using neutral beam etching than by using RIE-like condition, and the Vt shift at reduced Lgate is also suppressed. A damaged layer at high-k/Si interface by RIE-like condition is observed in the TEM image, which can correspond to the degradation in electrical characteristics. Furthermore, the proportional scaling of Ion versus Wfin indicates negligible S/D resistance due to good activation by Microwave annealing (MWA). In short, functional FinFETs were fabricated by Neutral beam etching (NBE) and Microwave annealing (MWA) for the first time, and these results pave ways for the techniques to be adopted in the advanced semiconductor processing. The SOI FinFETs demonstrate proportional scaling of on current versus the fin width and indicating that the S/D region is well activated by the microwave annealing method.

Porous low- k films, deposited using a plasma-enhanced chemical vapor deposition (PECVD) porogen-based process, were treated by H 2 /He plasma at varied temperatures ranging from 25 °C to 350 °C in this study. Two different plasma treatment reactors: capacitive coupling plasma (CCP) and remote plasma (RP) systems, were used to compare the impacts of H 2 /He plasma treatment on the porous low- k film. Experimental results indicate that H 2 /He plasma treatment in CCP system caused a larger degradation in low- k film's properties due to the physical-chemical reaction by H ions, radicals, and VUV photons as compared to that in RP system with only presence of H radicals. Additionally, the operation temperature of H 2 /He plasma treatment operated in the CCP and RP systems resulted in an adverse effect. H 2 /He plasma-treated low- k films operated in CCP system at elevated temperatures exhibited a large scission of Si–CH 3 groups, a large increase in k -value and leakage current, and a large degradation in breakdown field and TTF. However, the damage induced by H 2 /He plasma in RP system was alleviated by increasing the operation temperature. Additionally, as the operation temperature is raised to 350 °C, the positive effects with the reduction of k -value and the improvement of reliability were detected in H 2 /He plasma-treated low- k films. These enhanced properties are attributed to the removal of carbon-based porogen residues by He/H 2 plasma in RP system at high temperatures. Consequently, remote He/H 2 plasma treatment operated at high temperatures is a damage-free process for porous low- k films as it is used to strip resist during the fabrication of interconnects.

In this study, a double glass system with PbO base and ZnO base of Cu paste is designed, prepared and printed with narrow line screen printing process on polycrystalline Si solar cell which has already finished the back Al printing and deposition of double anti-reflection coatings (DARCs). And then, a two-step firing process is applied to sinter the front electrode and obtain the ohmic contact between front electrode and solar cell. The first step of firing is conducted in air atmosphere. In this process, PbO-based glass frit etched the DARCs and Ag recrystallized at the surface of Si, constructing the preliminary contact. The second step of firing is conducted in a reducing atmosphere (H 2 /N 2 = 5/95). In this process, the CuO is reduced into Cu which is sintered with ZnO based-glass. Ag nanoparticles recrystallized in the glass layer at interface due to the interactions between H 2 , Ag and PbO-based glass frit and the volatility of Pb, improve the Ohmic contact between electrode and solar cell. According to our investigation, a model of the reaction mechanisms in the double glass system of Cu paste in each sintering stage is proposed. And we have shown that Ohmic contact and good sheet resistance for the Cu front electrode with Pb-free could both be obtained by applying the newly-invented Cu paste and two steps of firing process. The lowest sheet resistance and contact resistance for such a Cu front electrode measured are 0.090 Ω/□ and 0.0040 Ω/□, respectively.

In this study, the plating and wetting ability of Cu/Ruthenium-Tungsten (RuW)/silicon oxide (SiO2) multi-layer stacks were investigated. RuW alloy films were prepared on a SiO2 layer by sputtering, followed by a deposition of a Cu thin film by electro-plating. Scanning electron microscopy (SEM) top view images shows that Cu films can be electroplated on RuW, with smaller Cu nuclei size but in a more highly concentrated and uniform distribution than Cu films electroplated on Ta or TaN. The rate of Cu nucleation decreases and larger Cu clusters were formed on the RuW alloy films with increasing W content. Cu/RuW/SiO2 samples were annealed at 400°C for 30min and then characterized using SEM. There were fewer pin holes on the surface of a pure Cu/Ru stack compared to Cu/RuW multilayers. Cu/RuW/SiO2 multi-layers had fewer pin holes than Cu/Ta/SiO2 structures processed under similar conditions. The wetting angle, measured by SEM, of Cu on a RuW substrate (43°) was still lower than that of Cu on a Ta substrate (123°), which suggests that the adhesion strength of Cu onto RuW alloy is better than that onto Ta. Preliminary studies of Cu diffusion through 25nm RuW layers at 650°C showed no Cu penetration into the underlying Si in a Cu/RuW/Si multi-layer test structure. Display Omitted Cu can be directly electroplated on varies ratio of RuW films with uniform nucleation.The wetting angle for adhesion ability of Cu onto RuW(60) film is better than that onto Ta.The amorphous Ru0.28W0.72 film is an alternative candidate for the Cu direct platable seedless barrier layer in the advanced copper metallization process.

Atomic layer deposited thin HfO2 film has been demonstrated to act as a pore-sealing layer and a Cu diffusion barrier layer used in porous low-k dielectrics. This study investigates the effect of annealing temperature on the electrical characteristics and reliability of the dielectric stacks with HfO2 and porous low-k films. The experimental results reveal that annealing improved electrical performance and reliability, but increased the dielectric constant. However, the resulting dielectric constant of the annealed HfO2/porous low-k dielectric stacks following oxygen plasma treatment was still lower than that of the dielectric stacks without annealing, indicating that annealing improved the properties of HfO2/porous low-k dielectric stacks. Annealing at 400°C improved electrical characteristics, reliability, and Cu barrier performance more than did annealing at 600°C because at 600°C annealing, the grain boundaries of the crystallized HfO2 film provide a conduction path and cause the breakage of the porous low-k film. However, the HfO2/porous low-k dielectric stacks that were annealed at 600°C exhibited greater resistance against damage by oxygen plasma. Display Omitted Effects of annealing temperature on HfO2/porous low-k dielectric stacks are investigated.Annealing HfO2/porous low-k dielectric stacks improved electrical characteristics and reliability.Annealing at 400°C anneal had a larger improvement annealing at 600°C.HfO2/porous low-k dielectric stack annealed at 600°C had a better resistance against oxygen plasma damage.

In this Letter, high-temperature ion implantation and low-temperature microwave annealing were employed to achieve maximum n-type active concentration, which can be fully activated in germanium. To use the characteristic of microwave annealing more effectively, two-step microwave annealing was also employed. In the first step annealing, a high-power (1200 W; 425 °C) microwave was used to achieve solid-state epitaxial regrowth (SPER) and enhance microwave absorption. In the second step of annealing, unlike in conventional thermal annealing, which requires a higher energy to activate the dopant, a low-power (900W;375 °C) microwave was used to achieve lowest sheet resistance 78Ω/□ and maximum active concentration 1.025×1020 P/cm3, which close to its solid solubility limit of 2×1020 P/cm3.

Selective Laser Melting (SLM) is a powder-based additive manufacturing which is capable of producing parts layer-by-layer from a 3D CAD model. The aim of this study is to adopt the selective laser melting technique to magnetic material fabrication. [1]For the SLM process to be practical in industrial use, highly specific mechanical properties of the final product must be achieved. The integrity of the manufactured components depend strongly on each single laser-melted track and every single layer, as well as the strength of the connections between them. In this study, effects of the processing parameters, such as the space distance of surface morphology is analyzed. Our hypothesis is that when a magnetic product is made by the selective laser melting techniques instead of traditional techniques, the finished component will have more precise and effective properties. This study analyzed the magnitudes of magnetic properties in comparison with different parameters in the SLM process and compiled a completed product to investigate the efficiency in contrast with products made with existing manufacturing processes.

In this study, colossal effective permittivity (e′ ∼ 50 000) dielectrics are attained in Mn and Nb co-doped SrTiO3-based capacitors, and the effective permittivity is explained in terms of an internal barrier layer (IBL) effect. Here, we use a combination of characterization techniques, including scanning transmission electron microscopy (STEM), electron energy loss spectroscopy (EELS), energy dispersive X-ray spectroscopy (EDS), and charge Deep Level Transition Spectroscopy (Q-DLTS) to confirm the presence of interfacial electronic traps in an air co-fired capacitor with Pt internal electrodes. The IBL was developed by an oxidative annealing process, leading to improved dielectric loss and breakdown voltages. The elemental mapping confirms that the dopant has a Mn-rich segregation layer in the grain boundaries and also at the electrode/ceramic interface. The EELS results reveal the valence change of manganese changed from a mixed Mn2+/Mn3+ to a mixed Mn3+/Mn4+ during an annealing process. The valence changes helps to enhance the Schottky barrier height at the grain boundaries, and this is quantified by a Capacitance–Voltage (C–V) analysis. Moreover, Q-DLTS results are presented to show the three electronic traps existing at IBL. All these changes with oxidative annealing are also discussed and related to the electrical and dielectric property trends.

In this study, two-step, low energy (2 keV + 1 keV) ion implantation and low-temperature microwave annealing (MWA) were employed to recover and activate boron implanted SiGe wafers. The boron was introduced by a combination of in situ doping during epi-growth (3.2 × 1020 cm−3) and a two-step ion implantation process (3 × 1015 cm−2 and 2 × 1015 cm−2). The activation of boron, which is close to the solid solubility limit in SiGe, was investigated following MWA or rapid thermal annealing. The thermal process was found to have the dominant effect on activation, but the SiGe composition also had an effect. For Ge content between 20% and 40%, Si 0.65 Ge 0.35 is an optimum alloy. Following implantation and annealing, boron distribution, sheet resistance, and mobility were checked to infer the activation level and defect evolution. A pre-amorphization implant using Ge ions has the best performance, and can effectively enhance the boron activation while preventing diffusion, when followed by MWA.

As-deposited CuInSe₂ thin films by electrodeposition method are usually accompanied with amorphous structure which is regarded detrimental for solar cell conversion efficiency. In this work, we proposed an annealing method under high pressure for improving the conversion efficiency of electrodeposited CuInSe₂ thin film solar cells, and the microstructure of high-pressure annealed CuInSe₂ films were also investigated. The annealing pressure was set from 100 kPa to 250 kPa, and the annealed CuInSe₂ thin films were then fabricated into solar cell using standard process. Field-emission scanning electron microscopy (FESEM) images show that CuInSe₂ films with higher annealing pressure demonstrate denser and smoother surface morphology. Results from X-ray diffraction (XRD) and Raman spectra indicate that annealing under high pressure enhanced the (1 1 2) preferential orientation of CuInSe₂ films and also eliminated binary Cu–Se phases. Finally, through annealing CuInSe₂ absorber layer under 200 kPa, the fill factor of the CuInSe₂ solar cell was found to be improved from 28.4% to 55% and the efficiency from 2.77% to 6.91%.

Recently, Thin Film Transistors (TFTs) have been studied widely because of potential applications in low cost, low-temperature process and flexible displays. They can be fabricated by easy processes based on solution methods. But the mobility of organic TFTs is lower and the threshold voltage is higher than amorphous Si TFTs. In order to enhance the channel mobility and satisfy with the requirement of low-cost fabrication, we prepare a low-cost, mask-free, reduced material wastage, deposited technology using transparent, directly printable, air-stable semiconductor slurries and dielectric solutions. In our investigations, we attempt to obtain a high performance and low-cost TFT via preparing materials, designing device structure, and using PZT inkjet-printing technology. A stable and non-precipitated metal oxide ink with appropriate doping was prepared for the fabrication of an InxZn1.5Sn1.0 (IZTO) by PZT inkjet-printing. The soluble direct-printing process is a powerful tool for material research and implies that the printable materials and the printing technology enable the use of all-printed low-cost flexible displays and other transparent electronic applications. Transparent materials including dielectric PVP, conductive carbon nanotube (CNT) and active IZTO were employed into the fabrication of our PZT inkjet-printing process. After annealed at 180 °C, The experimental all-printed TFT exhibit the carrier mobility of 0.194 cm2/Vs, sub-threshold slope of 20 V/decade, and the threshold voltage of 5 V, initially. All-inkjet-printed films have great transparency, potentially in transparent electronics and the transmittance pattern in visible part of the spectrum (400–700 nm) is over 80%.

Solar cell is one of the most popular alternative energies. The aim of this study is to construct an ohmic contact between front electrode and Si-based solar cell by a Newly-invented low-cost paste and low temperature sintering process. The core-shell of CucoreAgshell powders were prepared for making high solid content paste, then screen printing the fine line on laser-opening H-pattern silicon substrate and applying firing process. Because the silver coverage is more than 95% and silver nanoparticles start to melt at 200 °C. The shell of nanoparticles of silver not only is used to prevent copper from oxidized, but also connected core Cu particles for enhancing the conductivity of CucoreAgshell. TEM, EDS, SEM were used to examine the microstructure of CucoreAgshell. Fourpoint probe and transmission line model were employed to analyze the sheet resistance and the specific contact resistance. The lowest specific contact resistivity is 0.005 Ωcm2, sheet resistance is 0.0138 Ω/ and the lowest resistivity of front electrode measured is 2.65 × 10-5 Ωcm when CucoreAgshell paste with 94 wt% solid content was fired at 550 °C.

This paper investigates the properties of CuMn/Ru/SiO2. The optimal concentration of Mn in the CuMn alloy as a barrier layer in this structure is determined. The properties of CuMn/Ru/SiO2 are compared to those of CuMn/SiO2 and CuMn/Ta/SiO2. The electrical and material properties of CuMn (0–10 at.% Mn) alloy films deposited on SiO2, Ta, and Ru are studied. A diffusion barrier layer self-formed at the interface during annealing, and the growth behavior followed a logarithmic rate law. The microstructures of the CuMn films are analyzed using trans mission electron microscopy and are correlated with the electrical properties. After thermal treatment, only Cu–5 at.% Mn/SiO2 did not exhibit a diffusion of Cu atoms. After annealing, the thermal stability of films grown on Ru/SiO2 was better than that of films grown on SiO2 and Ta/SiO2. When a Ta or Ru layer was added, the Mn atoms diffused not only to the interface but also to the grain boundaries in the under layer and to the interface between the under layer and SiO2. The tolerance of Mn content increased when the Ru layer was used, and thus, CuMn/Ru prevented the diffusion of Cu after heat treatment at 600 $^{\circ}\hbox{C}$?> for 30 min.