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Land-use change not only affects habitat availability, it can also reduce population density and limit opportunities for interactions with conspecifics, further influencing species resilience to environmental challenges. For social species whose conspecific interactions are typically cooperative in nature, little is known about how land-use change influences demography and social behavior, and how this interaction impacts a species’ climatic niche. Here, we develop a spatially explicit, individual-based model to explore how land-use changes influence population size and niche width in social organisms through the Allee effect, the positive impact of higher population density on individual fitness. We then empirically test key model predictions by studying the distribution and cooperative behavior of burying beetles (Nicrophorus nepalensis) along elevational gradients in Taiwan. In support of our model predictions, we find that beetle densities are lower in areas of greater land-use change, making it harder for individuals in these hotter environments to form cooperative groups to compete against blowflies, their primary interspecific competitor. Consequently, the beetles’ lower distributional boundary is higher in areas with greater land-use change, indicating that the beetles’ thermal niche is reduced via Allee effects in human-altered landscapes. Ultimately, land-use change not only reduces habitat availability, it also shrinks the thermal niche of social species, making them more vulnerable to climate change.

How abiotic and biotic factors constrain distribution limits at the harsh and benign edges of species ranges is hotly debated, partly because macroecological experiments testing the proximate causes of distribution limits are scarce. It has long been recognized - at least since Darwin's On the Origin of Species - that a harsh climate strengthens competition and thus sets species range limits. Using thorough field manipulations along a large elevation gradient, we show the mechanisms by which temperature determines competition type, resulting in a transition from interference to exploitative competition from the lower to the upper elevation limits in burying beetles (Nicrophorus nepalensis). This transition is an example of Darwin's classic hypothesis that benign climates favor direct competition for highly accessible resources while harsh climates result in competition through resources of high rivalry. We propose that identifying the properties of these key resources will provide a more predictive framework to understand the interplay between biotic and abiotic factors in determining geographic range limits.

Power integrity has become increasingly important for the designs in 32 nm or below. This paper discusses a silicon-validated methodology for power delivery (PD) modeling and simulation. Many prior works have focused on PD analysis and optimization. However, none of them provided a comprehensive modeling methodology with postsilicon data to validate the use of the models. In this paper, we present PD system models that are able to achieve less than 10% deviation from the supply noise measurements on a 32-nm industrial double date-rate I/O design. Our models are able to capture the unique impacts of on-die inductance, state-dependent coupling capacitance, and die-package interaction. Those impacts are prominent for the designs in 32 nm or below but were considered negligible or even not noted in earlier technology nodes. Comparisons were made to quantify the impacts of different modeling strategies on supply noise prediction accuracy. This specifically provides designers insights in selecting appropriate models for PD analysis.

Accurately predicting power supply noise (PSN) induced jitter is crucial to link signal integrity analysis. PSN induced jitter becomes more severe with a decreased supply level, or increased design density. It exhibits strong time dependence due to power management technique employed in low-power design. For the first time, the bursty nature of PSN-induced jitter during power-state transition is accurately accounted for in full-link signal-integrity analysis. We present that power state transition frequency has a major impact on I/O link total jitter. This phenomenon that will be demonstrated with jitter simulations can be utilized to prevent over-design provided architecture-level wake-up behavior is determined.

In this paper, a detailed physical analysis and an analytical derivation of the degradation of the output resistance (Rout) observed in relatively long-channel laterally nonuniformly doped devices with halo implants are presented. Two-dimensional device simulations were performed, and the simulations show that the channel can be split into two uniformly doped transistors in series for the purpose of analysis. The lower doped bulk transistor is on the source side, while the higher doped halo transistor is toward the drain end. Based on this two-transistor analysis, a simple Rout degradation model is derived for implementation in a MOSFET compact model

We present new physically based effective mobility models for both electrons and holes in MOS accumulation layers. These models take into account carrier-carrier scattering, in addition to surface roughness scattering, phonon and fixed interface charge scattering, and screened Coulomb scattering. The newly developed effective mobility models show excellent agreement with experimental data over the range 1/spl times/10/sup 16/-4/spl times/10/sup 17/ cm/sup -3/ for which experimental data are available. Local-field dependent mobility models have also been developed for both electrons and holes, and they have been implemented in the two-dimensional (2-D) device simulators, PISCES and MINIMOS, thus providing for more accurate prediction of the terminal characteristics in deep submicron CMOS devices. In addition, transition region mobility models have been developed to account for the transition in the mobility in going from the accumulation layer in the gate-to-source overlap region to the inversion layer region in the channel.

For the first time, the tunneling current in silicon nMOS structures with ultra-thin gate oxides has been studied both by numerically solving Schrodinger's equation and by using the WKB approximation, which explicitly includes the size quantization effects in the inversion layers. The numerical solution employs first-order perturbation within the one-band effective-mass approximation to calculate the lifetime of an inversion-layer quasi-bound state. The good agreement in the tunneling currents estimated with these two methods justifies the use of the WKB approximation in the direct tunneling regime. The range of validity of the WKB approximation is also discussed.

Non-local electron transport in nMOSFET inversion layers has been studied by Monte Carlo (MC) simulations. Inversion layer quantization has been explicitly included in the calculation of density of states and scattering rate for low-energy electrons while bulk band structure is used to describe the transport of more energetic electrons. For uniform, high-lateral field conditions, the effects of quantization are less pronounced due to the depopulation of electrons in the lower-lying subbands. On the other hand, Monte Carlo results for carrier transport in spatially varying lateral fields (such as those in the inversion layer of MOSFETs) clearly indicate that depopulation of the low-lying subbands is less evident in the non-local transport regime. Quasi-2D simulations have shown that, at high transverse effective field, the inclusion of a quantization domain does have an impact on the calculated spatial velocity transient.

The array of thermal modeling tools demonstrated here provided a new methodology to improve design and reliability evaluations as we tackle the power-thermal issues with current IC design. Net-specific Tj and interconnect SH prediction, when applied on large megablock designs, lead to significant thermal margins and benefit for electromigration. The analysis here also highlighted challenges associated with device and interconnect scaling, especially the small-scale thermal interaction and power density increases. Global-local CAD approaches and research into nano-scale heat transfer are critical in making sure that future design can make efficient use of the silicon scaling that is afforded by Moore's law, as we enter the new era of scaling for energy-efficient processors [8].

This session presents novel approaches to modeling variability and technology optimization. The session begins with an invited paper by Christie et al., on rapid design flows for advanced technology path-finding. A rigorous approach to the dynamic large-scale stability of semiconductor circuits and devices is the subject of the second paper by Cappelluti et al., A proposal for breaking through the 60mV/dec. Subthreshold swing limit using ferroelectric materials is presented by Salahuddin and Datta. The role of high-k spacers in sub-20nm FinFETs is discussed next in a paper by Sachid et al., The rest of the session discusses variability issues and their impact on device design. The need to limit layout restrictions is presented by H. Onodera. H. Dadgour et al., will then address grain orientation effects in emerging Metal-Gate Devices. A study of Metal-Gate FinFET variability is presented next by O'uchi et al., This session concludes with a presentation on transport-based dopant mapping in advanced FinFets by Lansbergen et al.

Surface potential-based compact MOSFET models intended for circuit simulations are becoming mainstream. A critical building block for developing such models is a fast and accurate solution of the implicit surface potential equation. Here, we present a robust algorithm for the surface potential solution, with efficiency comparable to recently proposed analytic approximations and without any compromise in accuracy.

Predictive compact models have been developed to describe NQS effects and thermal noise in Intel's 90nm radio-frequency (RF) CMOS (Kuhn, et al., 2002). The physical approach enables modeling transistor performance from DC to RF with one single set of parameters. Quantum correction on classical induced-gate-noise model is observed for the first time in ultra-thin oxide technology.

This work describes the noise figure performance of CMOS transistors at the 90 nm technology node. Noise parameters are measured from 2-18 GHz, resulting in a minimum noise figure less than 2 dB across the range of measured frequencies for both NMOS and PMOS. Data is presented showing the effect of total gate width, gate length, and bias on the noise parameters.

A closed-form expression for the threshold voltage, V/sub t/, of MOSFETs fabricated with halo processes is described. The proposed approach accurately captures the length dependent V/sub t/ behavior under different drain and body bias conditions and temperature. In addition, the necessity of considering separate V/sub t/ expressions for current and capacitances is discussed. A doping transformation is employed to obtain equivalent channel dopings, necessary for charge-sheet models that do not rely on the threshold voltage concept.

The need to understand and predict MOS accumulation layer mobility has become increasingly important as MOS devices scale to the 100 nm gate length range. Indeed, the accumulation layer in the shallow source/drain extension in MOSFETs is becoming a significant part of the series resistance. Also, the accumulation layer is the major carrier transport layer in accumulation mode SOI MOSFETs and PMOS buried-channel MOSFETs. However, temperature dependent experimental data and accurate models for the accumulation layer mobility are not available. This paper reports for the first time accumulation layer mobility models for both electrons and holes. Also for the first time, we report experimental data for both electrons and holes over the important temperature range of 25-150°C for a range of doping concentrations from 1×10/sup 16/ to 4×10/sup 17/ cm/sup -3/. From the newly developed effective mobility models, compact and computationally efficient local mobility models have also been developed and implemented in the PISCES and MINIMOS 2D device simulators. Using the newly developed accumulation layer mobility models, a more accurate prediction of the device drive current has been made possible for both N-channel and P-channel deep submicron MOSFETs.

For the first time, it is rigorously shown that the source/drain partition of gate leakage current in a MOSFET is identical to that of inversion charge. This paper provides model developers a general recipe in addressing the partition issue and enables more consistent model parameter extraction methodology for MOSFETs in sub-100 nm technology.

The decreasing dimensions of IC devices is rendering the heat diffusion equation highly inaccurate for simulations of electrostatic discharge (ESD) phenomena. As dimensions of the heated region in the device are reduced far below 200 nm, neglecting the ballistic, sub-continuum nature of phonon conduction in the silicon lattice can strongly underpredict the temperature rise. This work integrates the phonon Boltzmann transport equation (BTE) in deep sub-micron silicon devices and presents a general methodology for solving the BTE. The approach developed is applicable to both Si and SOI devices and predicts temperature rises consistent with failure voltage measurements for practical devices.