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This article presents a study of two types of on-chip FPGA voltage sensors based on ring oscillators (ROs) and time-to-digital converter (TDCs), respectively. It has previously been shown that these sensors are often used to extract side-channel information from FPGAs without physical access. The performance of the sensors is evaluated in the presence of circuits that deliberately waste power, resulting in localized voltage drops. The effects of FPGA power supply features and sensor sensitivity in detecting voltage drops in an FPGA power distribution network (PDN) are evaluated for Xilinx Artix-7, Zynq 7000, and Zynq UltraScale+ FPGAs. We show that both sensor types are able to detect supply voltage drops, and that their measurements are consistent with each other. Our findings show that TDC-based sensors are more sensitive and can detect voltage drops that are shorter in duration, while RO sensors are easier to implement because calibration is not required. Furthermore, we present a new time-interleaved TDC design that sweeps the sensor phase. The new sensor generates data that can reconstruct voltage transients on the order of tens of picoseconds.

Physical unclonable functions (PUFs) have not only been suggested as a new key storage mechanism, but—in the form of so-called strong PUFs—also as cryptographic primitives in advanced schemes, including key exchange, oblivious transfer, or secure multi-party computation. This notably extends their application spectrum, and has led to a sequence of publications at leading venues such as IEEE S&P, CRYPTO, and EUROCRYPT in the past. However, one important unresolved problem is that adversaries can break the security of all these advanced protocols if they gain physical access to the employed strong PUFs after protocol completion. It has been formally proven that this issue cannot be overcome by techniques on the protocol side alone, but requires resolution on the hardware level—the only fully effective known countermeasure being so-called erasable PUFs. Building on this work, this paper is the first to describe a generic method of how any given silicon strong PUF with digital CRP-interface can be turned into an erasable PUF. We describe how the strong PUF can be surrounded with a trusted control logic that allows the blocking (or “erasure”) of single CRP. We implement our approach, which we call “GeniePUF,” on FPGA, reporting detailed performance data and practicality figures. Furthermore, we develop the first comprehensive definitional framework for erasable PUFs. Our work so re-establishes the effective usability of strong PUFs in advanced cryptographic applications, and in the realistic case, adversaries get access to the strong PUF after protocol completion. As an extension to earlier versions of this work, we also introduce a generalization of erasable PUFs in this paper, which we call programmable access-controlled PUFs (PAC PUFs). We detail their definition, and discuss various exemplary applications of theirs.

In this article, a novel interconnect technology is presented for the cost-effective and flexible design of asynchronous networks-on-chip. It delivers asynchrony in heterogeneous system integration while yielding low-energy on-chip data movement. The approach consists of both a lightweight asynchronous switch architecture (using transition-signaling protocols and bundled-data encoding) and a complete synthesis flow built on top of mainstream industrial CAD tools. For the first time, this article demonstrates compelling area, performance and power benefits when compared to a recent commercial synchronous switch, and the ability of the tool flow to correctly instantiate a complete and competitive network topology.

Multiple emerging computing technologies based on, e.g., graphene, spintronics, resistive RAM, quantum computing, and others are being developed to enhance the capabilities of logic devices and circuits. The rapid growth in these technologies is synchronized with the decline of Moore’s law, thus promises to herald the era of Beyond CMOS technologies with a significant improvement in energy efficiency, reliability, performance, and manufacturability. These devices enable very different computing paradigms, e.g., neuromorphic computing, non-Boolean computing, and in-memory computing, thus making these platforms an interesting playground for circuit and application-developers alike.

Physical Unclonable Functions (PUFs) are lightweight security primitives that exploit complex manufacturing variations in integrated circuits to extract secret keys. It is well-established that the unique keys generated by the mux-based arbiter PUF can be predicted accurately using logistic regression (LR), provided a set of challenge-response pairs (CRPs) are known. The integration of 28nm HKMG FeFET with CMOS technology has been shown to neither alter the switching behavior of the FeFET, nor affect the baseline CMOS. In this work, we present simulation results that discuss the possibility of using the FeFET to design “stronger” arbiter PUFs that can be reconfigured at least 6n times, where n represents the number of stages. Results from LR based attacks suggest that the training dataset may need to be updated after every reconfiguration cycle, preventing the adversary from collecting enough training data for each configuration within a reasonable amount of time for a security breach.

Physical Unclonable Functions (PUFs) have not only been suggested as new key storage mechanism, but --- in the form of so-called "Strong PUFs'' --- also as cryptographic primitives in advanced schemes, including key exchange, oblivious transfer, or secure multi-party computation. This notably extends their application spectrum, and has led to a sequence of publications at leading venues such as IEEE S&P, CRYPTO, and EUROCRYPT in the past[3,6,10,11,29, 41]. However, one important unresolved problem is that adversaries can break the security of all these advanced protocols if they gain physical access to the employed Strong PUFs after protocol completion [41]. It has been formally proven[49] that this issue cannot be overcome by techniques on the protocol side alone, but requires resolution on the hardware level --- the only fully effective known countermeasure being so-called Erasable PUFs. Building on this work, this paper is the first to describe a generic method how any given silicon Strong PUF with digital CRP-interface can be turned into an Erasable PUFs[36]. We describe how the Strong PUF can be surrounded with a trusted control logic that allows the blocking (or "erasure") of single CRPs. We implement our approach, which we call "GeniePUF", on FPGA, reporting detailed performance data and practicality figures. Furthermore, we develop the first comprehensive definitional framework for Erasable PUFs. Our work so re-establishes the effective usability of Strong PUFs in advanced cryptographic applications, and in the realistic case adversaries get access to the Strong PUF after protocol completion.

This paper presents a study of two types of on-chip FPGA voltage sensors based on ring oscillators (ROs) and time-to-digital converter (TDCs), respectively. The performance of these sensors is evaluated in the presence of circuits that deliberately waste power, resulting in localized voltage drops. The effects of FPGA power supply features and sensor sensitivity in detecting voltage drops in an FPGA power distribution network (PDN) are evaluated for Xilinx Artix-7 and Zynq UltraScale+ FPGAs. We show that the two sensor types are both able to detect supply voltage drops, and that their measurements are consistent with each other. However, we find that TDC-based sensors are more sensitive and can detect voltage drops that are shorter in duration, while RO sensors have a higher dynamic range and are easier to implement because calibration is not required.

Technology scaling of complementary metal–oxide–semiconductor has resulted in new thermal behavior where increase in operating temperature results in reduced circuit propagation delay. This paper exploits this inverse thermal dependence (ITD) for power, performance, and temperature optimization in single-core and multicore processor architectures for various thermally hot and cold applications. Since ITD increases the maximum achievable operating frequency of a processor at high temperatures, it is used to reduce the execution time of applications. Dynamic thermal management (DTM) techniques, such as activity migration (AM), dynamic voltage frequency scaling (DVFS), and throttling, are modified to leverage ITD to either enhance the performance or the energy efficiency. While recent work observed the ITD effect for 45- and 32-nm technologies, in this paper, we explore future technologies through predictive SPICE models for 20-, 14-, 10-, and 7-nm technologies. The results show that the ITD-aware techniques reduce the execution time, energy-delay product (EDP) and energy-delay-square product by up to 28%, 33%, and 48%, respectively. Moreover, the ITD-aware DVFS yields the lowest execution time while resulting in the most uniform thermal profile and thus enhanced reliability. Overall, the ITD-aware techniques reduce the execution time and EDP, both in combination with DTM techniques or stand-alone, especially at lower than nominal operating voltages.

Measuring timing signals of sub-picosecond has become an urgent need in today's high-speed electronics design. However, conventional timing measurement devices are either built with analog circuits that are hard to integrate with digital systems or differential delay-lines whose resolution is significantly impacted by the process variations of a circuit or environmental conditions. In this work, we present a novel all-digital timing measurement circuit: PVTMC, which for the first time, constructively leverages process variations to measure timing signals of sub-picosecond duration. We show that PVTMC achieves high resolution and robust performance against environmental fluctuations. A simple random search-based method is proposed to speed up the measurements and improve its accuracy. We also demonstrate that PVTMC is compatible with most prevalent CMOS technology nodes, as well as FPGA implementations due to the existence of process variations.

The power side-channel continues to be a major vulnerability in many critical systems. Numerous countermeasures have been proposed since its discovery as a serious vulnerability, including both hardware and software implementations. Each countermeasure has its own drawback, with some of the more popular countermeasures incurring 3-4x overhead in area and power. While this is acceptable for some devices, other lightweight devices can not tolerate this amount of overhead. In addition, most countermeasures are quite invasive to the design process, requiring modification to the design and additional validation. This work explores two relatively non-invasive countermeasures, both the detailed implementations and the interactions: 1) clock randomization, and 2) supply voltage noise, by real collecting power traces from a state-of-the-art FPGA board and using the Correlation Power Analysis (CPA) attack. Counter-attacks and their impact on the countermeasure efficacy are also explored. The key result is that the combined effects of the two countermeasures is greater than the impact of either countermeasure when used independently.

Sensing platforms are becoming batteryless to enable the vision of the Internet of Things, where trillions of devices collect data, interact with each other, and interact with people. However, these batteryless sensing platforms—that rely purely on energy harvesting—are rarely able to maintain a sense of time after a power failure. This makes working with sensor data that is time sensitive especially difficult. We propose two novel, zero-power timekeepers that use remanence decay to measure the time elapsed between power failures. Our approaches compute the elapsed time from the amount of decay of a capacitive device, either on-chip Static Random-Access Memory (SRAM) or a dedicated capacitor. This enables hourglass-like timers that give intermittently powered sensing devices a persistent sense of time. Our evaluation shows that applications using either timekeeper can keep time accurately through power failures as long as 45s with low overhead.

On-chip True Random Number Generators (TRNG) are important cryptographic primitives in a variety of applications. In advanced CMOS process technologies, intra-die variations in transistor parameters bias the TRNG and degrade the statistics of the bit stream generated. In this work, we present a stochastic model for metastability based TRNG circuit incorporating both the impact of intra-die variations and thermal noise. The stochastic model is used to estimate the expected entropy out of a TRNG at a given process corner for variations in channel length and threshold voltage. We use the stochastic model to study the impact of variations on three lightweight post-processing techniques: von Neumann corrector, XOR function, and PRESENT cipher. The expected bit rate out of von Neumann corrector, number of XOR stages required for entropy extraction and the number of iterations for using PRESENT encryption are estimated for various process corners using the probabilistic entropy values. These analyses are further extended to different device sizing and operating voltage to explore the optimum trade-off between entropy extraction and energy overhead. A combination of HSPICE circuit simulation using 32 nm Predictive Technology models and stochastic modeling in MatLab show that XOR function and von Neumann corrector have an energy overhead ranging from 0.012pJ/bit to 0.15pJ/bit at the cost of decreased yield and bit-rate respectively. PRESENT cipher provides robust entropy extraction by increasing the number of encryption iterations from 1 for $\mu/\sigma(Leff) to 3 for $\mu/\sigma(Leff)>8\%$ . With a maximum of 2.52pJ/bit PRESENT provides a more energy efficient solution compared to AES for entropy extraction in power constrained applications.

Physical unclonable functions (PUFs) are circuits that produce outputs determined by random physical variations from fabrication. The PUF studied in this paper utilizes the variation sensitivity of static random access memory (SRAM) data retention voltage (DRV), the minimum voltage at which each cell can retain state. Prior work shows that DRV can uniquely identify circuit instances with 28% greater success than SRAM power-up states that are used in PUFs [1] . However, DRV is highly sensitive to temperature, and until now this makes it unreliable and unsuitable for use in a PUF. In this paper, we enable DRV PUFs by proposing a DRV-based hash function that is insensitive to temperature. The new hash function, denoted DRV-based hashing (DH), is reliable across temperatures because it utilizes the temperature-insensitive ordering of DRVs across cells, instead of using the DRVs in absolute terms. To evaluate the security and performance of the DRV PUF, we use DRV measurements from commercially available SRAM chips, and use data from a novel DRV prediction algorithm. The prediction algorithm uses machine learning for fast and accurate simulation-free estimation of any cell’s DRV, and the prediction error in comparison to circuit simulation has a standard deviation of 0.35 mV. We demonstrate the DRV PUF using two applications—secret key generation and identification. In secret key generation, we introduce a new circuit-level reliability knob as an alternative to error correcting codes. In the identification application, our approach is compared to prior work and shown to result in a smaller false-positive identification rate for any desired true-positive identification rate.

High-resolution time-to-digital converters (TDCs) are important time measurement circuits in various high-speed electronic systems. The development of semiconductor technology improves the resolution of TDCs, but also introduces negative impact like process variations. Since modern TDCs are designed to achieve resolution of picosecond magnitude, process variations become a big concern. In this work, we present a configurable compact algorithmic TDC (CCATDC), that can digitize the analog time input into binary codes. Moreover, the proposed CCATDC can be configured to mitigate the impact from random process variations and transient noise. To achieve real-time circuit calibration and measurement, a Backpropagation based Machine Learning framework is proposed to configure the CCATDC circuit. In common TDC usage, it is assumed that the order of two timing signals is known, while in practice this is hardly true with input time difference of picosecond level. To overcome this problem, we propose a bidirectional design that is applicable to any input order. This method also increases the throughput by 50%. Experimental results demonstrate that our proposed CCATDC can achieve high conversion resolution (

An asynchronous high-performance low-power 5-port network-on-chip (NoC) router is introduced. The proposed router integrates low-latency input buffers using a circular FIFO design, and a novel end-to-end credit-based virtual channel (VC) flow control for a replicated switch architecture. This asynchronous router is then compared to an AMD synchronous router, in a realistic advanced 14nm FinFET library. This is the first such comparison, to the best of our knowledge, using a real synchronous router baseline already fabricated in several commercial products. Initial post-synthesis pre-layout experiments show dominating results for the asynchronous router, when compared to the synchronous router. In particular, 55% less area and 28% latency improvement are observed for the asynchronous implementation. Also, 88% and 58% savings in idle and active power, respectively, are obtained.

Numerous sensors are currently deployed in modern processors to collect thermal information for fine-grained dynamic thermal management (DTM). Due to process variation and silicon aging, on-chip thermal sensors require periodic calibration before use in DTM. However, the calibration cost for thermal sensors can be prohibitively high as the number of on-chip sensors increases. In this paper, a model which is suitable for online calculation is employed to estimate the temperatures of multiple sensor locations on the silicon die. The estimated sensor and actual sensor thermal profile show a very high similarity with correlation coefficient ${\sim}{\rm 0.9}$ for most tested benchmarks. Our calibration approach combines potentially inaccurate temperature values obtained from two sources: temperature readings from thermal sensors and temperature estimations using system performance counters. A data fusion strategy based on Bayesian inference, which combines information from these two sources, is demonstrated along with a temperature estimation approach using performance counters. The average absolute error of the corrected sensor temperature readings is ${ and the standard deviation of error is less than ${ for tested benchmarks.

We discuss numerical modeling attacks on several proposed strong physical unclonable functions (PUFs). Given a set of challenge-response pairs (CRPs) of a Strong PUF, the goal of our attacks is to construct a computer algorithm which behaves indistinguishably from the original PUF on almost all CRPs. If successful, this algorithm can subsequently impersonate the Strong PUF, and can be cloned and distributed arbitrarily. It breaks the security of any applications that rest on the Strong PUF's unpredictability and physical unclonability. Our method is less relevant for other PUF types such as Weak PUFs. The Strong PUFs that we could attack successfully include standard Arbiter PUFs of essentially arbitrary sizes, and XOR Arbiter PUFs, Lightweight Secure PUFs, and Feed-Forward Arbiter PUFs up to certain sizes and complexities. We also investigate the hardness of certain Ring Oscillator PUF architectures in typical Strong PUF applications. Our attacks are based upon various machine learning techniques, including a specially tailored variant of logistic regression and evolution strategies. Our results are mostly obtained on CRPs from numerical simulations that use established digital models of the respective PUFs. For a subset of the considered PUFs-namely standard Arbiter PUFs and XOR Arbiter PUFs-we also lead proofs of concept on silicon data from both FPGAs and ASICs. Over four million silicon CRPs are used in this process. The performance on silicon CRPs is very close to simulated CRPs, confirming a conjecture from earlier versions of this work. Our findings lead to new design requirements for secure electrical Strong PUFs, and will be useful to PUF designers and attackers alike., National Science Foundation (U.S.) (Grant CNS 0923313), National Science Foundation (U.S.) (Grant CNS 0964641)

Power gating (PG) is an effective power efficiency improvement technique. Future general-purpose graphics processing units (GPGPUs) will likely feature hundreds of compute units (CUs) and be power constrained, which leads to serious challenges to existing PG methodologies. In this paper, we propose novel design-time and run-time techniques to effectively implement power gating in future GPGPUs. Based on industrial models/measurement facilities, we show that designers must consider run-time parallelism within potential applications while implementing power gating designs to avoid incurring unnecessary design overheads. By scaling measurements from a real 28nm GPGPU to a hypothetical future 10nm node, we show that a PG granularity of 16 CU/cluster achieves 99% peak run-time performance without the excessive 53% design-time area overhead of per-CU PG. We also demonstrate that a run-time power management algorithm that is aware of the PG granularity leads to up to 18% additional performance through frequency-boosting under thermal-design power (TDP) constraints.

More and more security attacks today are perpetrated by exploiting the hardware: memory errors can be exploited to take over systems, side-channel attacks leak secrets to the outside worlds, weak random number generators render cryptography ineffective, etc. At the same time, many of the tenets of efficient design are in tension with guaranteeing security. For instance, classic secure hardware does not allow to optimize common execution patterns, share resources, or provide deep introspection. We provide brief descriptions of three recently-exposed hardware vulnerabilities along with extensive references for background and to learn more about these areas. Specifically, we first discuss the Rowhammer problem in modern DRAM chips, which enables attackers to circumvent memory isolation, and other potential vulnerabilities due to aggressive memory technology scaling. We next describe hardware Trojans implemented below the gate level, which can resist most detection techniques, and other manufacturing vulnerabilities in security primitives. Finally, we explain side channels that can achieve very large information leakage capacities, and various potential defenses against them. We conclude by noting that the intersection of hardware design and security attacks and countermeasures will continue to present a rich area for research and development for many years to come.

Since the introduction of the first side-channel analyses in academia about 15 years ago, several physical attacks have been presented that exploit side-channel leakages to break implementations of cryptographic algorithms. This article deals with the same physical property of electronic devices, but focuses on the art of tailoring it for constructive uses. More precisely, two scenarios, i.e., hardware Trojans and IP watermarking, are illustrated in which the designer of an electronic circuit can add functionality by considering side channels as part of the available design space. Both applications use the same concept, i.e., deliberately leaking a secret through a side channel while keeping the introduced side channel hidden from adversaries and attackers. This article provides a broad overview of the existing works for both applications and should serve as a comprehensible introduction to the underlying field of research. This includes many subtle details that have not been discussed in literature yet, including existing shortcomings and possible improvements to the existing works. The solutions summarized in this article provide general guidelines for theorists and practitioners to use side channels constructively to achieve designs that are robust against detection and removal. Furthermore, we present an entirely new design of a Trojan side-channel. This architecture demonstrates the potential of a Trojan side-channel that is neatly tailored to the targeted implementation. The new design removes all non-invasive starting points a third party could use to analyze or get access to the secret-channel.

Source code plagiarism has become a serious problem for the industry. Although there exist many software solutions for comparing source codes, they are often not practical in the embedded environment. Today's microcontrollers have frequently implemented a memory read protection that prevents a verifier from reading out the necessary source code. In this paper, we present three verification methods to detect software plagiarism in embedded software without knowing the implemented source code. All three approaches make use of side-channel information that is obtained during the execution of the suspicious code. The first method is passive, i.e., no previous modification of the original code is required. It determines the Hamming weights of the executed instructions of the suspicious device and uses string matching algorithms for comparisons with a reference implementation. In contrast, the second method inserts additional code fragments as a watermark that can be identified in the power consumption of the executed source code. As a third method, we present how this watermark can be extended by using a signature that serves as a proof-of-ownership. We show that particularly the last two approaches are very robust against code-transformation attacks.

Harnessing unique physical properties of integrated circuits to enhance hardware security and IP protection has been extensively explored in recent years. Physical unclonable functions (PUFs) can sense inherent manufacturing variations as chip identifications. To enable the integration of PUFs into low-power and security applications, we study the impacts of process technology and supply voltage scaling on arbiter-based PUF circuit design. A Monte Carlo-based statistical analysis has demonstrated that advanced technologies and reduced supply voltage can improve the PUF uniqueness due to increased delay sensitivity. A linear regression approach has been leveraged to generate PUF delay profile by factoring in device, supply voltage and temperature variations. An accurate SVM-based software modeling analysis is used to verify the PUF additive delay behavior. Finally, postsilicon validation on arbiter-based PUF test chips in 45 nm SOICMOS technology has been correlated to simulation results and the inconsistency has been discussed. The test chips can resist the basic support vector machine attack due to the dynamic circuit effects and the limitation of our delay model.

Period jitter plays a critical role in global clock distribution design, because it directly impacts the time available for logic operations between sequential elements. Moreover, time-varying supply noise injected in global clock drivers can worsen the timing margin of critical paths by modulating period jitter. In the planning stage of global clock distribution for a high-end microprocessor, it is very critical to differentiate and understand the impacts of different design parameters on period jitter. However, it is hard to achieve due to complex relationship among different independent/dependent design parameters: supply noise amplitude, supply noise frequency, clock driver size, physical structures of interconnects, number of clock stages, temperature, process corners, etc. In this paper, we propose sets of analytical expressions which accurately model the behavior of supply noise induced period jitter of global binary clock trees without losing the details of clock distribution design parameters. These accurate expressions and their derivation process are used to provide detailed insight into the relationships between period jitter of binary clock distribution and distribution design parameters with several examples. Also detailed design guidelines for binary clock trees are presented.

Intermittently powered applications create a need for low-cost security and privacy in potentially hostile environments, supported by primitives including identification and random number generation. Our measurements show that power-up of SRAM produces a physical fingerprint. We propose a system of fingerprint extraction and random numbers in SRAM (FERNS) that harvests static identity and randomness from existing volatile CMOS memory without requiring any dedicated circuitry. The identity results from manufacture-time physically random device threshold voltage mismatch, and the random numbers result from runtime physically random noise. We use experimental data from high-performance SRAM chips and the embedded SRAM of the WISP UHF RFID tag to validate the principles behind FERNS. For the SRAM chip, we demonstrate that 8-byte fingerprints can uniquely identify circuits among a population of 5,120 instances and extrapolate that 24-byte fingerprints would uniquely identify all instances ever produced. Using a smaller population, we demonstrate similar identifying ability from the embedded SRAM. In addition to identification, we show that SRAM fingerprints capture noise, enabling true random number generation. We demonstrate that a 512-byte SRAM fingerprint contains sufficient entropy to generate 128-bit true random numbers and that the generated numbers pass the NIST tests for runs, approximate entropy, and block frequency.

Embedded systems present significant security challenges due to their limited resources and power constraints. This paper focuses on the issues of building secure embedded systems on reconfigurable hardware and proposes a security architecture for embedded systems (SAFES). SAFES leverages the capabilities of reconfigurable hardware to provide efficient and flexible architectural support for security standards and defenses against a range of hardware attacks. The SAFES architecture is based on three main ideas: (1) reconfigurable security primitives; (2) reconfigurable hardware monitors; and (3) a hierarchy of security controllers at the primitive, system and executive level. Results are presented for reconfigurable AES and RC6 security primitives and highlight the value of such an architecture. This paper also emphasizes that reconfigurable hardware is not just a technology for hardware accelerators dedicated to security primitives as has been focused on by most studies but a real solution to provide high-security and high-performance for a system.

In this paper, hybrids based on current-sensing and repeaters are proposed for on-chip interconnects in an effort to overcome the limitations of these techniques. A novel receiver for current-sensing results in static power savings and allows an easier transition from current-sensing to traditional full rail voltage signals. Measurements of hybrids on a 0.18-m CMOS technology show significant gains over repeater insertion in delay across wire lengths. Hybrids can also be used in placement constrained and low-noise scenarios to achieve delay and power benefits.

While hardware obfuscation has been used in industry for many years, very few scientific papers discuss layout-level obfuscation. The main aim of this paper is to start a discussion about hardware obfuscation in the academic community and point out open research problems. In particular, we introduce a very flexible layout-level obfuscation tool that we use as a case study for hardware obfuscation. In this obfuscation tool, a small custom-made obfuscell is used in conjunction with a standard cell to build a new obfuscated standard cell library called Obfusgates. This standard cell library can be used to synthesize any HDL code with standard synthesis tools, e.g. Synopsis Design Compiler. However, only obfuscating the functionality of individual gates is not enough. Not only the functionality of individual gates, but also their connectivity, leaks important important information about the design. In our tool we therefore designed the obfuscation gates to include a large number of "dummy wires". Due to these dummy wires, the connectivity of the gates in addition to their logic functionality is obfuscated. We argue that this aspect of obfuscation is of great importance in practice and that there are many interesting open research questions related to this.

As CMOS technology scales down towards nanometer regime and the supply voltage approaches the threshold voltage, increase in operating temperature results in increased circuit current, which in turn reduces circuit propagation delay. This paper exploits this new phenomenon, known as inverse thermal dependence (ITD) for power, performance, and temperature optimization in processor architecture. ITD changes the maximum achievable operating frequency of the processor at high temperatures. Dynamic thermal management techniques such as activity migration, dynamic voltage frequency scaling, and throttling are revisited in this paper, with a focus on the effect of ITD. Results are obtained using the predictive technology models of 7nm, 10nm 14nm and 20nm technology nodes and with extensive architectural and circuit simulations. The results show that based on the design goals, various design corners should be re-investigated for power, performance and energy-efficiency optimization. Architectural simulations for a multi-core processor and across standard benchmarks show that utilizing ITD-aware schemes for thermal management improves the performance of the processor in terms of speed and energy-delay-product by 8.55% and 4.4%, respectively.

To maintain reliable operation, task allocation for many-core processors must consider the heat interaction of processor cores and network-on-chip routers in performing task assignment. Our approach employs reinforcement learning, machine learning algorithm that performs task allocation based on current core and router temperatures and a prediction of which assignment will minimize maximum temperature in the future. The algorithm updates prediction models after each allocation based on feedback regarding the accuracy of previous predictions. Our new algorithm is verified via detailed many-core simulation which includes on-chip routing. Our results show that the proposed technique is fast (scheduling performed in

We discuss the question of how physical statements can be proven over digital communication channels between two parties (a "prover" and a "verifier") residing in two separate local systems. Examples include: (i) "a certain object in the prover's system has temperature X°C", (ii) "two certain objects in the prover's system are positioned at distance X", or (iii) "a certain object in the prover's system has been irreversibly altered or destroyed". As illustrated by these examples, our treatment goes beyond classical security sensors in considering more general physical statements. Another distinctive aspect is the underlying security model: We neither assume secret keys in the prover's system, nor do we suppose classical sensor hardware in his system which is tamper-resistant and trusted by the verifier. Without an established name, we call this new type of security protocol a "virtual proof of reality" or simply a "virtual proof" (VP). In order to illustrate our novel concept, we give example VPs based on temperature sensitive integrated circuits, disordered optical scattering media, and quantum systems. The corresponding protocols prove the temperature, relative position, or destruction/modification of certain physical objects in the prover's system to the verifier. These objects (so-called "witness objects") are prepared by the verifier and handed over to the prover prior to the VP. Furthermore, we verify the practical validity of our method for all our optical and circuit-based VPs in detailed proof-of-concept experiments. Our work touches upon, and partly extends, several established concepts in cryptography and security, including physical unclonable functions, quantum cryptography, interactive proof systems, and, most recently, physical zero-knowledge proofs. We also discuss potential advancements of our method, for example "public virtual proofs" that function without exchanging witness objects between the verifier and the prover.

Physically Unclonable Functions PUFs are used for generating unique signatures from the complex manufacturing variations in integrated circuits. However, the majority of PUFs have been shown to be vulnerable to modeling attacks. In this work, we take a closer look at the vulnerability of feed-forward arbiter PUFs towards a combined side-channel and modeling attack using data measured from our 32nm test chips. The side-channel information from the feed-forward PUF construction is used as a catalyst for improving the performance of modeling attacks. This hybrid attack helps to push the prediction accuracies to very high limits >98.5%, especially for larger PUF circuits. The hybrid attack yields around 7% improvement in prediction rates when compared to a conventional modeling attack mounted under the presence of error-inflicted challenge-response pairs.

The Bistable Ring BR Physical Unclonable Function PUF is a newly proposed hardware security primitive in the PUF family. In this work, we comprehensively evaluate its resilience against Machine Learning ML modeling attacks. Based on the success of ML attacks, we propose XOR strategies to enhance the security of BR PUFs. Our results show that the XOR BR PUF with more than four parallel BR PUFs is able to resist the ML modeling methods in this work. We also evaluate the other PUF metrics of reliability, uniqueness and uniformity, and find that the XOR function is also effective in improving the uniformity of BR PUFs.

This paper describes a novel deterministic globally-asynchronous locally-synchronous (GALS) methodology called "synchro-tokens". Wrappers around the synchronous blocks keep the system globally asynchronous while ensuring that each transition, although arriving at a nondeterministic time, is sensed by the synchronous block during a deterministic cycle of the local clock. This determinism facilitates debug and test methodologies, such as the use of stored-pattern testers, which are effective only when the system behavior is predictable and repeatable. Applications of synchro-tokens to GALS systems with two or more synchronous blocks and one or more asynchronous data channels are shown. Synchro-tokens supports both pipelined and unpipelined channels and a variety of clock generation methodologies. Novel schematic level designs of the wrapper components in a 180-nm technology are used to compare the performance of several different deterministic GALS design styles.

Despite recent advances in smart card technology, most modern smart cards continue to rely on card readers for power and clocking, creating a potential security gap. In this paper, we present an energy-aware smart card architecture that operates using an embedded battery and crystal. This low-power VLSI system is continually active and provides enhanced security through periodic internal update when the card is detached from a reader. Our architecture achieves reduced power consumption by deactivating the majority of its circuitry, including an embedded microcontroller, for the vast majority of the card's lifetime. A proof-of-concept prototype implementation of the architecture has been developed including register-transfer-level and gate-level designs which have been synthesized to silicon. To permit extended operation for up to 18 months, critical design logic has been implemented using ultralow-power (adiabatic) circuit techniques.

Error-correcting convolutional codes provide a proven mechanism to limit the effects of noise in digital data transmission. Although hardware implementations of decoding algorithms, such as the Viterbi algorithm, have shown good noise tolerance for error-correcting codes, these implementations require an exponential increase in very large scale integration area and power consumption to achieve increased decoding accuracy. To achieve reduced decoder power consumption, we have examined and implemented decoders based on the reduced-complexity adaptive Viterbi algorithm (AVA). Run-time dynamic reconfiguration is performed in response to varying communication channel-noise conditions to match minimized power consumption to required error-correction capabilities. Experimental calculations indicate that the use of dynamic reconfiguration leads to a 69% reduction in decoder power consumption over a nonreconfigurable field-programmable gate array implementation with no loss of decode accuracy.

This paper presents a differential current-sensing technique as an alternative to existing circuit techniques for on-chip interconnects. Using a novel receiver circuit, it is shown that, delay-optimal current-sensing is a faster (20% on an average) option as compared to the delay-optimal repeater insertion technique for single-cycle wires. Delay benefit for current-sensing increases with an increase in wire width. Unlike repeaters, current-sensing does not require placement of buffers along the wire, and hence, eliminates any placement constraints. Inductive effects are negligible in differential current-sensing. Current-sensing also provides a tighter bound on delay with respect to process variations. However, current-sensing has some drawbacks. It is power inefficient due to the presence of static-power dissipation. Current-sensing is essentially a low-swing signaling technique, and hence, it is sensitive to full swing aggressor noise.

Signal processing algorithms and architectures can use dynamic reconfiguration to exploit variations in signal statistics with the objectives of improved performance and reduced power. Parameters provide a simple and formal way to characterize incremental changes to a computation and its computing mechanism. This paper develops a framework for dynamic parameterization and applies it to MPEG-4 motion estimation. A novel motion estimation architecture facilitates the dynamic variation of parameters to achieve power-compression tradeoffs. Our work shows that parameter variation in motion estimation helps achieve power reduction by an order of magnitude, trading off higher compression for lower power. The magnitude of the tradeoffs depends on the input signal variation. The monitoring of input and output signal statistics and subsequent variation of parameters is accomplished by a hardware controller. To provide the controller with a model of the parameter space and corresponding measures in terms of power and performance, a configuration sample space graph is developed. This graph identifies the parameters which present the best power-performance tradeoffs. The controller samples the operating environment to select the appropriate parameters. This reduces the average power consumption by 40% for 2% loss in compression. Four other signal dependent computations: (1) 2D Discrete Cosine Transform, (2) Lempel-Ziv lossless compression, (3) 3D graphics light rendering, and (4) Viterbi decoding are briefly discussed to demonstrate the applicability of dynamic reconfiguration.

Trends in complementary metal-oxide-semiconductor (CMOS) technology and very large scale integration architectures are causing interconnect to play an increasing role in overall performance, power consumption, and design effort. Traditionally, repeaters are used for driving long onchip interconnects. However, recent studies indicate that repeaters are using increasing area, power, and design resources and are inherently limited in how much they can improve the performance (Adler and Friedman, 1998), (Sylvester and Keutzer, 1999), (Cong and Pan, 1999). The unidirectionality of repeaters also limits their applicability in multisourced lines. This paper presents a new circuit called the Booster that compares favorably with repeaters for driving long lines in terms of area, performance, power, and placement sensitivity. Boosters also have the advantage of being bidirectional and providing a low impedance termination to improve signal integrity. Driver edge rates are reduced and peak power is drastically reduced compared to repeaters, thus, improving signal integrity and mitigating inductive effects. Boosters are shown to be more than 20% faster for driving a variety of interconnect loads over conventional repeaters in a 0.16-/spl mu/m CMOS technology. Boosters are typically inserted three times less frequently than repeaters for optimal performance, resulting in fewer boosters for driving the same interconnect lengths and, hence, saving on area, power, and placement effort. Computer-aided design tools for global interconnect synthesis need to support a wider variety of circuit techniques such as boosters. Other exotic circuit techniques such as differential, dynamic, or low-swing techniques require significantly more custom circuit design, noise analysis, extra timing signals, or extra power supplies and are, hence, cumbersome for automatic interconnect synthesis tools. In contrast, the proposed boosters can be inserted on lines in a straightforward manner much like repeaters. Based on analytical delay models, we derive rules for insertion and sizing of boosters that can easily be incorporated into an interconnect synthesis tool. We formulate design rules that determine: 1) the number of boosters needed; 2) their placements; and 3) device sizes for driving a given interconnect load. The primary objective function is minimizing delay and then area and power. Power analysis is slightly more complex than for repeaters so we present a systematic design approach. A placement sensitivity analysis comparing boosters and repeaters is used to study the effects of realistic placement constraints that arise in microprocessor floorplans. We conclude by discussing various design tradeoffs between repeater and booster-based interconnect designs. We then present other potential applications of boosters in domino logic designs, multisource/multisink buses, and field programmable gate array interconnection network designs in addition to conventional point-to-point interconnection lines.

Direct placement of Phase Change Materials (PCMs) on the chip has been recently explored as a passive temperature management solution. PCMs provide the ability to store large amounts of heat at a close-to-constant temperature during the phase change (solid to liquid and vice versa). This latent heat capacity can be used to provide higher performance while reducing hot spots. Detailed modeling of the phase change behavior is essential for the design and evaluation of systems with PCM. This paper proposes an accurate phase change model that is integrated into the commonly used thermal simulation tool, HotSpot. It also provides validation of the proposed model by carrying out computational fluid dynamics (CFD) simulations using COMSOL Multiphysics ® . This paper also explores the impact of PCM properties on the thermal profile of a processor, and demonstrates that PCM material choices can affect peak temperatures by up to 20.1°C. Experimental results show that dynamic policy decisions change dramatically when using the proposed detailed phase change model, as prior simpler PCM models can substantially over/under-estimate temperature and PCM melting duration. The proposed model helps design more effective dynamic management policies and enables realistic evaluation of systems with PCM.

In the last 5 years, there has been a considerable increase in research and awareness of security and privacy issues in implantable medical devices. This has been driven by the rapid introduction and deployment of an increasing diversity of medical devices. Although wearable and clinical devices are also of interest, the implantable nature of many recent devices significantly increases risks as well as engineering challenges. This talk will use several case studies to review the multi-disciplinary process in which vulnerabilities are analyzed, disclosed, and repaired. Business incentives and regulations play an important role in the overall process. Technical challenges include energy harvesting, side-channel protection, lightweight crypto, personalization, wireless communications, security/safety tradeoffs, and human factors. Several open research areas will be discussed.