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Power MOSFET heavy ion-induced Single Event Burnout tests were performed jointly by representatives of the Aerospace Corporation, NASA Goddard, NWSC Crane and Rockwell International. For the most part, presented are the results of the burnout threshold and cross section characterizations performed on n-channel power MOSFETs, however a small amount of p-channel data is also included. In addition, data on the effect of temperature, gate bias, total dose and inductive loading on MOSFET Single Event Burnout sensitivity is preferred. At the time of the test effort, 'radiation hardened' devices were being developed by International Rectifier and RCA/GE. The heavy-ion-induced burnout test results on available samples of these devices are also incorporated for comparison to the commercial and JEDEC versions tested.

A radiation-hard CMOS/SOS technology has been used to fabricate a complex LSI circuit containing over 2200 transistors. The circuit is an eight bit wide arithmetic and logic unit (ALU) slice. This paper describes the results of electrical, temperature, and radiation tests on the ALU circuit. An instruction cycle-time of less than 240 ns was achieved for nominal operation at +11V and 25 C. This time increases to 300 ns at 125 C. After irradiation to 1 mega rad. (SI) under bias, operation was degraded only slightly. The 25 C and 125 C postradiation cycle times were within 320 and 360 ns, respectively. Radiation tolerance from part to part and lot to lot excellent, thus demonstrating the applicability of radiation hard CMOS/SOS to LSI circuitry. (Author), Presented at the Conference on Magnetism and Magnetic Materials (23rd) 8-11 Nov 77, Minneapolis, MN.