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Nonreciprocal electrical transport, characterized by an asymmetric relationship between current and voltage, plays a crucial role in modern electronic industries. Recent studies have extended this phenomenon to superconductors, introducing the concept of the superconducting diode effect (SDE). The SDE is characterized by unequal critical supercurrents along opposite directions. Due to the requirement on broken inversion symmetry, the SDE is commonly accompanied by electrical magnetochiral anisotropy (eMCA) in the resistive state. Achieving a magnetic field-free SDE with field tunability is pivotal for advancements in superconductor devices. Conventionally, the field-free SDE has been achieved in Josephson junctions by intentionally intercalating an asymmetric barrier layer. Alternatively, internal magnetism was employed. Both approaches pose challenges in the selection of superconductors and fabrication processes, thereby impeding the development of SDE. Here, we present a field-free SDE in FeTe0.7Se0.3 (FTS) junction with eMCA, a phenomenon absent in FTS single nanosheets. The field-free property is associated with the presence of a gradient oxide layer on the upper surface of each FTS nanosheet, while the eMCA is linked to spin-splitting arising from the absence of inversion symmetry. Both the SDE and eMCA respond to magnetic fields with distinct temperature dependencies. This work presents a versatile and straightforward strategy for advancing superconducting electronics.

Bit-level sparsity in neural network models harbors immense untapped potential. Eliminating redundant calculations of randomly distributed zero-bits significantly boosts computational efficiency. Yet, traditional digital SRAM-PIM architecture, limited by rigid crossbar architecture, struggles to effectively exploit this unstructured sparsity. To address this challenge, we propose Dyadic Block PIM (DB-PIM), a groundbreaking algorithm-architecture co-design framework. First, we propose an algorithm coupled with a distinctive sparsity pattern, termed a dyadic block (DB), that preserves the random distribution of non-zero bits to maintain accuracy while restricting the number of these bits in each weight to improve regularity. Architecturally, we develop a custom PIM macro that includes dyadic block multiplication units (DBMUs) and Canonical Signed Digit (CSD)-based adder trees, specifically tailored for Multiply-Accumulate (MAC) operations. An input pre-processing unit (IPU) further refines performance and efficiency by capitalizing on block-wise input sparsity. Results show that our proposed co-design framework achieves a remarkable speedup of up to 7.69x and energy savings of 83.43%., Comment: Accepted by DAC'24

Nonlinear Hall effect (NLHE) holds immense significance in recognizing the band geometry and its potential applications in current rectification. Recent discoveries have expanded the study from second-order to third-order nonlinear Hall effect (THE), which is governed by an intrinsic band geometric quantity called the Berry Connection Polarizability (BCP) tensor. Here we demonstrate a giant THE in a misfit layer compound, (SnS)${1.17}$(NbS$_2$)$_3$. While the THE is prohibited in individual NbS$_2$ and SnS due to the constraints imposed by the crystal symmetry and their band structures, a remarkable THE emerges when a superlattice is formed by introducing a monolayer of SnS. The angular-dependent THE and its scaling relationship indicate that the phenomenon could be correlated to the band geometry modulation, concurrently with the symmetry breaking. The resulting strength of THE is orders of magnitude higher compared to recent studies. Our work illuminates the modulation of structural and electronic geometries for novel quantum phenomena through interface engineering.

Processing-in-memory (PIM), as a novel computing paradigm, provides significant performance benefits from the aspect of effective data movement reduction. SRAM-based PIM has been demonstrated as one of the most promising candidates due to its endurance and compatibility. However, the integration density of SRAM-based PIM is much lower than other non-volatile memory-based ones, due to its inherent 6T structure for storing a single bit. Within comparable area constraints, SRAM-based PIM exhibits notably lower capacity. Thus, aiming to unleash its capacity potential, we propose DDC-PIM, an efficient algorithm/architecture co-design methodology that effectively doubles the equivalent data capacity. At the algorithmic level, we propose a filter-wise complementary correlation (FCC) algorithm to obtain a bitwise complementary pair. At the architecture level, we exploit the intrinsic cross-coupled structure of 6T SRAM to store the bitwise complementary pair in their complementary states ($Q/\overline{Q}$), thereby maximizing the data capacity of each SRAM cell. The dual-broadcast input structure and reconfigurable unit support both depthwise and pointwise convolution, adhering to the requirements of various neural networks. Evaluation results show that DDC-PIM yields about $2.84\times$ speedup on MobileNetV2 and $2.69\times$ on EfficientNet-B0 with negligible accuracy loss compared with PIM baseline implementation. Compared with state-of-the-art SRAM-based PIM macros, DDC-PIM achieves up to $8.41\times$ and $2.75\times$ improvement in weight density and area efficiency, respectively., Comment: 14 pages, to be published in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)

Electronic correlation and reconstruction are two important factors that play a critical role in shaping the magnetic and electronic properties of correlated low-dimensional systems. Here, we report a competition between the electronic correlation and structural reconstruction in La1-xSrxTiO3/SrTiO3 heterostructures by modulating material polarity and interfacial strain, respectively. The heterostructures exhibit a critical thickness (tc) at which a metal-to-insulator transition (MIT) abruptly occurs at certain thickness, accompanied by the coexistence of two- and three-dimensional (2D and 3D) carriers. Intriguingly, the tc exhibits a V-shaped dependence on the doping concentration of Sr, with the smallest tc value at x = 0.5. We attribute this V-shaped dependence to the competition between the electronic reconstruction (modulated by the polarity) and the electronic correlation (modulated by strain), which are borne out by the experimental results, including strain-dependent electronic properties and the evolution of 2D and 3D carriers. Our findings underscore the significance of the interplay between electronic reconstruction and correlation in the realization and utilization of emergent electronic functionalities in low-dimensional correlated systems.

Significant strides have been made in enhancing the accuracy of Multi-View Stereo (MVS)-based 3D reconstruction. However, untextured areas with unstable photometric consistency often remain incompletely reconstructed. In this paper, we propose a resilient and effective multi-view stereo approach (MP-MVS). We design a multi-scale windows PatchMatch (mPM) to obtain reliable depth of untextured areas. In contrast with other multi-scale approaches, which is faster and can be easily extended to PatchMatch-based MVS approaches. Subsequently, we improve the existing checkerboard sampling schemes by limiting our sampling to distant regions, which can effectively improve the efficiency of spatial propagation while mitigating outlier generation. Finally, we introduce and improve planar prior assisted PatchMatch of ACMP. Instead of relying on photometric consistency, we utilize geometric consistency information between multi-views to select reliable triangulated vertices. This strategy can obtain a more accurate planar prior model to rectify photometric consistency measurements. Our approach has been tested on the ETH3D High-res multi-view benchmark with several state-of-the-art approaches. The results demonstrate that our approach can reach the state-of-the-art. The associated codes will be accessible at https://github.com/RongxuanTan/MP-MVS.

Ratchet motion of superconducting vortices, which is a directional flow of vortices in superconductors, is highly useful for exploring quantum phenomena and developing superconducting devices, such as superconducting diode and microwave antenna. However, because of the challenges in the quantitative characterization of the dynamic motion of vortices, a phase diagram of the vortex ratchet motion is still missing, especially in the superconductors with low dimensional structures. Here we establish a quantitative phase diagram of the vortex ratchet motion in a highly anisotropic superlattice superconductor, (SnS)1.17NbS2, using nonreciprocal magnetotransport. The (SnS)1.17NbS2, which possesses a layered atomic structure and noncentrosymmetry, exhibits nonreciprocal magnetotransport in a magnetic field perpendicular and parallel to the plane, which is considered a manifest of ratchet motion of superconducting vortices. We demonstrated that the ratchet motion is responsive to current excitation, magnetic field and thermal perturbation. Furthermore, we extrapolated a giant nonreciprocal coefficient ({\gamma}), which quantitatively describes the magnitude of the vortex ratchet motion, and eventually established phase diagrams of the ratchet motion of the vortices with a quantitative description. Last, we propose that the ratchet motion originates from the coexistence of pancake vortices (PVs) and Josephson vortices (JVs). The phase diagrams are desirable for controlling the vortex motion in superlattice superconductors and developing next-generation energy-efficient superconducting devices.

Among various types of neuromorphic devices towards artificial intelligence, the electrochemical synaptic transistor emerges, in which the channel conductance is modulated by the insertion of ions according to the history of gate voltage across the electrolyte. Despite the striking progress in exploring novel channel materials, few studies report on the ferromagnetic metal-based synaptic transistors, limiting the development of spin-based neuromorphic devices. Here, we present synaptic modulation of both conductivity as well as magnetism based on an electrochemical transistor with a metallic channel of ferromagnetic CoPt alloy. We first demonstrate its essential synaptic functionalities in the transistor, including depression and potentiation of synaptic weight, and paired-pulse facilitation. Then, we show a short- to long-term plasticity transition induced by different gate parameters, such as amplitude, duration, and frequency. Furthermore, the device presents multilevel and reversible nonvolatile states in both conductivity and coercivity. The results demonstrate simultaneous modulation of conductivity and magnetism, paving the way for building future spin-based multifunctional synaptic devices.

The performance and efficiency of running large-scale datasets on traditional computing systems exhibit critical bottlenecks due to the existing "power wall" and "memory wall" problems. To resolve those problems, processing-in-memory (PIM) architectures are developed to bring computation logic in or near memory to alleviate the bandwidth limitations during data transmission. NAND-like spintronics memory (NAND-SPIN) is one kind of promising magnetoresistive random-access memory (MRAM) with low write energy and high integration density, and it can be employed to perform efficient in-memory computation operations. In this work, we propose a NAND-SPIN-based PIM architecture for efficient convolutional neural network (CNN) acceleration. A straightforward data mapping scheme is exploited to improve the parallelism while reducing data movements. Benefiting from the excellent characteristics of NAND-SPIN and in-memory processing architecture, experimental results show that the proposed approach can achieve $\sim$2.6$\times$ speedup and $\sim$1.4$\times$ improvement in energy efficiency over state-of-the-art PIM solutions., Comment: 15 pages, accepted by SCIENCE CHINA Information Sciences (SCIS) 2022

Triangles are the basic substructure of networks and triangle counting (TC) has been a fundamental graph computing problem in numerous fields such as social network analysis. Nevertheless, like other graph computing problems, due to the high memory-computation ratio and random memory access pattern, TC involves a large amount of data transfers thus suffers from the bandwidth bottleneck in the traditional Von-Neumann architecture. To overcome this challenge, in this paper, we propose to accelerate TC with the emerging processing-in-memory (PIM) architecture through an algorithm-architecture co-optimization manner. To enable the efficient in-memory implementations, we come up to reformulate TC with bitwise logic operations (such as AND), and develop customized graph compression and mapping techniques for efficient data flow management. With the emerging computational Spin-Transfer Torque Magnetic RAM (STT-MRAM) array, which is one of the most promising PIM enabling techniques, the device-to-architecture co-simulation results demonstrate that the proposed TC in-memory accelerator outperforms the state-of-the-art GPU and FPGA accelerations by 12.2x and 31.8x, respectively, and achieves a 34x energy efficiency improvement over the FPGA accelerator., Comment: arXiv admin note: substantial text overlap with arXiv:2007.10702