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In this work, it is demonstrated that the normal degradation of positive threshold voltage ( ${V}_{\text {TH}}{)}$ shift of flexible low-temperature poly-Si (LTPS) thin-film transistors (TFTs) during bending stress, which increases with bending cycles, as well as a similar degradation occurring spontaneously after the removal of mechanical stress, which depends on the idle time, can be unified as the same extrinsic phenomenon. This extrinsic degradation originates from the air ambient and depends on the operation lifetime, including both stress time and idle time. It is in contrast to the intrinsic degradation of negative ${V}_{\text {TH}}$ shift that occurs under the same bending stress but in a vacuum or an inert condition. A degradation model is proposed, which includes both extrinsic and intrinsic degradation.

The dynamic ${R}_{ \mathrm{\scriptscriptstyle ON}}$ degradation in AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) with different passivation layers (SiSi3N4 or Si3N4/ZrO2 stack) under off-, semi-on, and ON-state stress have been investigated in this work. Under the OFF-state stress of 40 V, a 20% reduction in the maximum drain current has been observed in devices passivated with Si{3}N{4}, along with a degraded ${R}_{ \mathrm{\scriptscriptstyle ON}}$ that is 1.42 times higher than the initial ${R}_{ \mathrm{\scriptscriptstyle ON}}$ . In contrast, devices passivated with Si3N4 or Si3N4/ZrO2 stack have only shown a 2% reduction, and the ${R}_{ \mathrm{\scriptscriptstyle ON}}$ degradation is only 1.03 times higher than the initial ${R}_{ \mathrm{\scriptscriptstyle ON}}$ . This can be attributed to the different interface states present in the two devices. According to the multifrequency $\vphantom {_{\int _{\text {a}}}}~{C}$ – ${V}$ curves, the Si3N4/GaN-cap interface trap density is in the range of $2\times 10^{{13}}$ – $5.5\times 10^{{13}}$ from ${E}_{C}-{0.47}$ to ${E}_{C}-{0.37}$ eV, and ZrO2/GaN-cap interface trap density is in the range of $2.7\times 10^{{12}}$ – $1.2\times 10^{{13}}$ from ${E}_{C}-{0.47}$ to ${E}_{C}-{0.31}$ eV. Under the semi-on state stress, the dynamic ${R}_{ \mathrm{\scriptscriptstyle ON}}$ degradation exhibits a “bell-shaped” behavior in the Si3N4 or Si3N4/ZrO2 stack passivated sample. Arrenhius plots indicate that the sample passivated by Si3N4 has an activation energy of 0.06 eV, while the sample passivated by Si3N4 or Si3N4/ZrO2 stack has an activation energy of 0.16 eV, which means a deeper trap distribution. The ${R}_{ \mathrm{\scriptscriptstyle ON}}$ degradation under semi-on/ ON-state stress in Si3N4 or Si3N4/ZrO2 passivated devices can be attributed to the hot-electron-related injection mechanism. Device designers must consider the trade-off between the high breakdown voltage (BV) and the ${R}_{ \mathrm{\scriptscriptstyle ON}}$ degradation in Si3N4 or Si3N4/ZrO2 passivated devices.

An ultrathin body and buried oxide (UTBB) SOI MOSFETs with novel non-LDD source/drain extensions are proposed, where highly conductive paths are induced by positive charges locally distributed in the buried oxide (BOX) connecting the channel and respective source and drain. TCAD simulation shows that the performance of the proposed MOSFET is superior to conventional UTBB MOSFETs of the same footprint in terms of drain-induced barrier lowering (DIBL), subthreshold swing (SS), and off-state current. Even with much relaxed device dimensions, such as thicker silicon body and/or BOX either with or without introducing a ground plane (GP), it can still achieve higher driving current and similar short-channel effect (SCE) immunity as the conventional UTBB MOSFETs. Such advantages of the proposed MOSFETs are due to better gate electrostatics over the channel benefited from the novel source/drain extensions.

This article investigates the effects of different kinds of trap states on the degradation of polycrystalline silicon (poly-Si) thin-film transistors (TFTs) under alternating current (ac) gate pulse bias stress. P-type TFTs with different ON-state and subthreshold characteristics are fabricated, and thus, different distributions of donor-like tail states and deep states are achieved. The decrease of ON-state current is the dominant degradation phenomena for all the TFTs due to trap state generation occurring during the pulse rising edges. TFTs with higher donor-like trap states show severe degradation. It is attributed to the higher transient lateral electric field and hole concentration due to the higher donor-like deep state density, while acceptor-like trap states do not contribute to the degradation of p-type poly-Si TFTs under ac gate bias stress.