555 results on '"Wambacq, Piet"'
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2. Introduction
3. A Background-Calibrated Digital Subsampling Polar Transmitter
4. A Background-Calibrated Subsampling PLL for Phase/Frequency Modulation
5. A Digital-to-Time-Converter-Based Subsampling PLL for Fractional Synthesis
6. Summary and Conclusions
7. Design Considerations for High-Datarate Low-Power 60 GHz TX Front-Ends
8. Digitally-Modulated Polar Transmitters in 40 nm CMOS
9. 60 GHz TX Front-Ends in Advanced CMOS Technologies with Improved Back-Off Efficiencies
10. Introduction
11. Challenges of Digitally Modulated Transmitter Implementation at Millimeter Waves
12. Resistive Charge-Based Transmitter
13. Capacitive Charge-Based Transmitter
14. Introduction
15. Incremental-Charge-Based Operation
16. A 33 dBm, >30% PAE GaN Power Amplifier Based on a Sub-Quarter-Wavelength Balun for 5G Applications
17. Conclusion
18. Layout and Post-layout Simulations
19. Introduction
20. Background
21. Top-Level Design
22. Design and Simulation Results
23. A Composite AlGaN/cGaN Back Barrier for mm-Wave GaN-on-Si HEMTs
24. Introduction
25. Digital Subsampling Phase Lock Techniques for Frequency Synthesis and Polar Transmission
26. Digitally-Modulated Polar Transmitters in 40 nm CMOS
27. 60 GHz TX Front-Ends in Advanced CMOS Technologies with Improved Back-Off Efficiencies
28. Summary and Conclusions
29. Design Considerations for High-Datarate Low-Power 60 GHz TX Front-Ends
30. Low-Power Millimeter Wave Transmitters for High Data Rate Applications
31. Conclusions
32. Design and Analysis of a 4.2 mW 4 K 6–8 GHz CMOS LNA for Superconducting Qubit Readout
33. RF linearity trade-offs for varying T-gate geometries of GaN HEMTs on Si
34. The Promise of 2-D Materials for Scaled Digital and Analog Applications
35. Foreword: Building on 70 Years of Innovation in Solid-State Circuit Design
36. 4.1 A 16GHz, $41\text{kHz}_{\text{rms}}$ Frequency Error, Background-Calibrated, Duty-Cycled FMCW Charge-Pump PLL
37. Design of a 10.56-Gb/s 64-QAM Polar Transmitter at 60 GHz in 28-nm CMOS
38. Fast: An Efficient High-Level Dataflow Simulator of Mixed-Signal Front-Ends of Digital Telecom Transceivers
39. Motivation, Context and Objectives
40. A 120–140-GHz LNA in 250-nm InP HBT
41. Weakly nonlinear behavior of basic analog building blocks
42. Basic terminology
43. Measurements of basic nonlinearities of transistors
44. MOS transistor models for distortion analysis
45. Silicon bipolar transistor models for distortion analysis
46. Volterra series and their applications to analog integrated circuit design
47. Description of nonlinearities in analog integrated circuits
48. Calculation of harmonics and intermodulation products
49. Introduction
50. Substrate Noise Coupling from Digital to Analog Circuits in Mixed-Signal Integrated Circuits
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