555 results on '"Wambacq, Piet"'
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2. Introduction
3. A Background-Calibrated Digital Subsampling Polar Transmitter
4. A Background-Calibrated Subsampling PLL for Phase/Frequency Modulation
5. A Digital-to-Time-Converter-Based Subsampling PLL for Fractional Synthesis
6. Summary and Conclusions
7. Design Considerations for High-Datarate Low-Power 60 GHz TX Front-Ends
8. Digitally-Modulated Polar Transmitters in 40 nm CMOS
9. 60 GHz TX Front-Ends in Advanced CMOS Technologies with Improved Back-Off Efficiencies
10. Introduction
11. Challenges of Digitally Modulated Transmitter Implementation at Millimeter Waves
12. Resistive Charge-Based Transmitter
13. Capacitive Charge-Based Transmitter
14. Introduction
15. Incremental-Charge-Based Operation
16. A 33 dBm, >30% PAE GaN Power Amplifier Based on a Sub-Quarter-Wavelength Balun for 5G Applications
17. A Composite AlGaN/cGaN Back Barrier for mm-Wave GaN-on-Si HEMTs
18. Conclusion
19. Layout and Post-layout Simulations
20. Introduction
21. Background
22. Top-Level Design
23. Design and Simulation Results
24. Design and Analysis of a 4.2 mW 4 K 6–8 GHz CMOS LNA for Superconducting Qubit Readout
25. Introduction
26. Digital Subsampling Phase Lock Techniques for Frequency Synthesis and Polar Transmission
27. Digitally-Modulated Polar Transmitters in 40 nm CMOS
28. 60 GHz TX Front-Ends in Advanced CMOS Technologies with Improved Back-Off Efficiencies
29. Summary and Conclusions
30. Design Considerations for High-Datarate Low-Power 60 GHz TX Front-Ends
31. Low-Power Millimeter Wave Transmitters for High Data Rate Applications
32. Conclusions
33. RF linearity trade-offs for varying T-gate geometries of GaN HEMTs on Si
34. The Promise of 2-D Materials for Scaled Digital and Analog Applications
35. Foreword: Building on 70 Years of Innovation in Solid-State Circuit Design
36. 4.1 A 16GHz, $41\text{kHz}_{\text{rms}}$ Frequency Error, Background-Calibrated, Duty-Cycled FMCW Charge-Pump PLL
37. Design of a 10.56-Gb/s 64-QAM Polar Transmitter at 60 GHz in 28-nm CMOS
38. Substrate Noise Coupling from Digital to Analog Circuits in Mixed-Signal Integrated Circuits
39. Fast: An Efficient High-Level Dataflow Simulator of Mixed-Signal Front-Ends of Digital Telecom Transceivers
40. Motivation, Context and Objectives
41. Theoretical Angular Resolution of Forward-Looking MIMO-SAR Systems
42. A 120–140-GHz LNA in 250-nm InP HBT
43. A 28nm 6.5-8.1GHz 1.16mW/qubit Cryo-CMOS System-an-Chip for Superconducting Qubit Readout
44. A 39-GHz 18.5-mW LNA with T/R switch, 15.4-dB gain, -2.2dBm IIP3, 5.6-dB NF, for a 5G in-cabin basestation in 22-nm FD-SOI
45. Weakly nonlinear behavior of basic analog building blocks
46. Basic terminology
47. Measurements of basic nonlinearities of transistors
48. MOS transistor models for distortion analysis
49. Silicon bipolar transistor models for distortion analysis
50. Volterra series and their applications to analog integrated circuit design
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