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SmartSiCTM technology enables the supply of cost-effective and high-quality substrates to support the manufacturing of Silicon Carbide (SiC) Power Devices and the transition to High Volume Manufacturing (HVM) [1]. As detailed in [2] SmartSiCTM is prepared using a poly-crystalline handle wafer, it combines the benefit from both an optimized high quality epi-ready 4H-SiC layer and an ultra high conductivity handle material. Smart CutTM technology can be extended to SiC 200mm substrates and first SmartSiCTM 200mm sample has been prepared [2].SmartSiCTM substrates crystal quality is inherited by donor wafers [1, 2] and do not require a systematic control, enabling a new defects monitoring strategy, focusing on surface defects.This paper describes how a commercially available DUV inspection system was utilized for high sensitivity, high-throughput inspections of 150 and 200 mm 4H-SiC and SmartSiCTM substrates, for the HVM environment. The KLA Surfscan® SP A2 unpatterned wafer inspection system offers the opportunity to complement other inspection technologies to optimize SiC substrate defect control, with low threshold detection, below 150 nm.

The Smart CutTM process offers an advantageous opportunity to provide a large number of performance-improved SiC substrates for power electronics. The crystalline quality and the electrical activation of the 4H-SiC transferred layer are then at stake when it comes to the power device reliability. In this study, we find that the H+ ion implantation used for the Smart CutTM process leads to electrical deactivation of dopants and partially disorders the material. The transferred layer fully recovers its initial crystalline quality after a 1300°C anneal, with no further evolution beyond this temperature. At this point however, the n-type dopants are still inactive. The dopant reactivation occurs in the same temperature range than that of implanted nitrogen: between 1400°C and 1700°C. After 1700°C, the initial doping level of bulk SiC is recovered.

The relaxation of tensile strain in fully depleted (FD) strained silicon-on-insulator (SSOI) by means of ion implantation is experimentally demonstrated in this work. This could enable SiGe p-channel field-effect transistors (pFETs) with high compressive strain (after ion implantation and Ge condensation) to be formed together with Si n-channel field-effect transistors (nFETs) with high tensile strain on the same substrate. From simulations in advanced technology node, 0.8% strain of nFETs and −0.9% strain of pFETs in fin structures can provide saturation drain current and peak ${G}_{\text {m}}$ enhancements of ~20%–30%. ${f}_{\text {T}}$ and ${f}_{\text {max}}$ benefit greatly from strain across the entire range of ${V}_{\text {G}}$ , with their peak values increasing significantly, thus allowing SSOI devices to meet 5G targets. In addition, forward back-bias shifts ${f}_{\text {T}}$ and ${f}_{\text {max}}$ curves toward lower $\boldsymbol \vert {V}_{\text {G}}\boldsymbol \vert $ , enabling reduced power consumption at the same high performance and providing better linearity. Hence, the ability to form highly strained nFETs and pFETs together on a common FD-SSOI substrate paves the way for it to become the ultimate high-performance complementary metal-oxide-semiconductor (CMOS) platform for 5G RF and logic circuits. The relaxation of the tensile strain is demonstrated and documented in Part I. A novel Comb-like device architecture to further enhance the SSOI electrical and RF performance is provided in Part II.

Abstract— To support 3D Sequential integration with a cost-effective layer transfer, SmartCut™ process at low temperature (below 500 °C) is proposed. Excellent SOI & BOX layer thickness uniformities are demonstrated, while layer integrity, electron and hole mobility performances are already compliant with development grade requirements. Keywords—SmartCut, 3D Integration, Low Temperature, CMOS I. SmartCut Proposal for 3D Sequential Integration In support of the semiconductor evolution, 3D integration is considered, addressing several challenges: integration of multiple types of devices including specialized components, continuous footprint reduction as well as optimization of performance and cost [1]. However, a key challenge for 3D integration, shown on Figure 1 reported in reference [2], is the preparation of a top tier device using as handle surface a fully processed bottom tier device. Hence, the top tier device thermal budget needs to be reduced to avoid degradation of the bottom devices [3]. A mandatory 500 °C thermal budget limitation for 3D Sequential Top layer transfer and MOSFET fabrication is then considered [2, 4]. In order to take advantage of the SmartCut process to transfer at reduced cost (i.e. avoiding a conventional but costly SOI bonding & grinding process) a high quality, highly uniform crystalline layer, we propose the use of a new Low Temperature SmartCut process as an alternative for 3D integration. This paper reports on our findings from such transfer demonstrations on bare handle materials, including for the first time SOI-like layer electrical characterization results. II. Low Temperature SmartCut for 3D Integration For 3D integration, SmartCut process is adapted as schematically shown on Figure 2 in order to transfer at low temperature ultra-thin layers compatible with fully depleted requirements. This process option includes the use of engineered, epitaxial processed donor wafers. The epitaxial process on conventional bulk material allows creation of a first Silicon-Germanium layer, to be used as an etch stop layer after SmartCut splitting. Then a subsequent Si layer, defined accordingly to the SOI film thickness target, is epitaxied. Implant, surface preparation, bonding, splitting process steps, all being compliant with maximum 500 °C low temperature requirement, benefit from conventional FD-SOI experience. Finishing process includes selective etching to recover SOI layer [5]. Then a dedicated curing process step is considered in order to optimize SOI layer electrical properties. Silicon Phase Epitaxial Regrowth (SPER) as described in reference [6] is proposed. Figure 3 highlights such low temperature layer transfer process on a patterned handle wafer. Picture is obtained after SmartCut splitting process step. A visual defect free layer is obtained. III. Low Temperature SOI Performance on Bare Handle wafer The SOI layer thickness variability, over the full spatial wavelength spectrum from device to wafer scale, is driven by the donor epitaxy performance. Figure 4 shows Atomic Force Microscopy (AFM) roughness performance, through 30x30 µm² scan. RMS of 1.0 and 0.9 Å are measured on high and low temperature process options respectively. Best in class performance is then obtained thanks to Low Temperature SmartCut. Figure 5 shows (a) BOX and (b) SOI layers ellipsometry thickness mapping, on a 12 nm SOI / 20 nm BOX sample. BOX layer variability is primarily driven by thermal oxide growth, thus demonstrating a within wafer uniformity << 10 A. SOI layer thickness variability is mainly driven by epitaxy performance on the engineered donor wafer. Figure 6 shows typical KLA Tencor SP3 @ 65 nm threshold defect mapping, as measured on 12 / 20 nm low temperature R&D sample. Micro-defect density on this early development product already demonstrates less than 0.1 defect / cm² performance. Then Figure 7 compares PsiMOS measured electron and hole mobility in the SOI layer using High and Low Temperature SmartCut processes. A as low as 10% mobility performance difference between both processes vintage is already demonstrated. IV. Conclusion To support 3D sequential integration, layer transfer at low temperature (< 500 °C) is demonstrated thanks to an adapted SmartCut process. Next research step will confirm this capability with low temperature layer transfer on patterned substrate for 3DS device assessment. V. References [1] J. Macri, Proc. IEEE S3S Conference, 2018 [2] L. Brunet et al., Technical Digest – IEDM Conference, 2018, pp 7.2.1 – 7.2.4 [3] A. Vandooren et al., Proc. IEEE S3S Conference, 2018 [4] C. Fenouillet-Beranger et al., Proc. IEDM Conf., 2014. [5] J. Widiez et al. ECS Trans., 2014, vol. 64(5), pp. 35-48 [6] G. Gaudin et al., ECS J. Solid. State. Sci Tech., 2(12), 2013, pp 534 - 538 Figure 1

Strained silicon-on-insulator (SSOI) is a promising platform for 5G, which will require both high-performance and low-power complementary metal–oxide–semiconductor (CMOS) devices. Hence, it is important to understand the behavior of strain in SSOI at deeply scaled dimensions. We thus present a simulation study of SSOI technology, where the strain profiles of “fins” with different dimensions and layer thicknesses are analyzed. We discover, for the first time, that a buried oxide (BOX) as thin as 10–15 nm is able to effectively memorize the strain. It is also able to retain the strain under annealing up to 1000 °C, a result verified by the Raman measurements. Such a thin BOX enables a good back-gate control for dynamic threshold voltage ( ${V}_{\text{t}}$ ) tuning of SSOI transistors. The ability to have a good performance enhancement (from strain), and dynamic ${V}_{\text{t}}$ tunability (from thin BOX) makes SSOI favorable for 5G mixed-signal applications.

For the first time, ion implant was used to partially relax the tensile strain by half in the fully-depleted (FD) strained SOI (SSOl) so that SiGe pFETs with a higher compressive strain can be realized at a fixed Ge composition. This enables the co-integration of highly tensile-strained Si nFETs and compressive-strained SiGe pFETs on the same substrate, achieving significant improvement in electrical performance over the unstrained counterpart verified by both experiment and simulation results. We also propose a Comb-like strained SOI architecture to further boost RF performance, demonstrating peak $G_{\mathrm{m}}$ improved by 47% over unstrained n-type FinFET SOI, as well as an improvement of 22% and 36% for $f_{\mathrm{T}}$ and $f_{\max}$ , respectively, over n-type FinFETs SSOI.

Top tier devices in a 3D sequential integration are optimized using a low temperature process flow $( . Bi-axial tensile strained silicon is transferred without strain relaxation to boost the top tier nmos device performance by 40-50% over the unstrained silicon devices, recovering the performance loss from the low temperature processing when using extension-less device integration. Excimer laser anneal is also shown to effectively activate both n-type and p-type dopants in the extension of thin silicon film devices using optimized, CMOS compatible, laser exposure conditions. Laser anneal is fully compatible with a replacement metal gate (RMG) process flow and with selective source/drain (SD) epitaxy. The dopant activation level is preserved during the entire process flow which results in similar $\mathrm{I}_{\mathrm{on}}-\mathrm{I}_{\mathrm{off}}$ device performance for devices with laser and spike anneals. Excimer laser anneal benefits also from improved control short channel effects over spike annealing due to low dopant diffusion.

3-D sequential integration requires top MOSFETs processed at a low thermal budget, which can impair the device reliability. In this paper, top junctionless (JL) devices are fabricated with a maximum processing temperature of 525 °C. The devices feature high k/metal replacement gate and low-temperature Si:P and SiGe:B 60% raised source and drain for nMOS and pMOS fabrication, respectively. Device matching, analog, and RF performance of the top tier devices are in-line with the state-of-the-art Si technology processed at high temperature (>1000 °C). JL devices operate at reduced electric field and can meet in specification reliability (10-year reliable operation at ${V}_{\textsf {G}}= {V}_{\textsf {th}}+ 0.6$ V, 125 °C), even without the use of “reliability” anneal. The top Si layer is transferred on CMOS planar bulk wafers with W metal-1 interconnects, using a SiCN to SiCN direct wafer bonding. Comparison with silicon-on-insulator devices fabricated with the same low-temperature flow shows no impact on device electrical performance from the Si layer transfer.

The carrier scattering mechanisms are quantitatively examined for UTB Ge-OI pMOSFETs. It is confirmed that the μ fluctuation is dominant for Ge-OI pMOSFETs thinner than ~5 nm and the μ ph /μ sr are dominant for thicker channels of >~8 nm.

Beyond conventional FinFet & FD-SOI device architectures, Complementary FET (CFET) is considered. To support this 3D approach, improving integration, manufacturing and paving the way to performance booster introduction, engineered substrates are proposed. Double SOI material availability for sampling is demonstrated with FinFet compliant layer thicknesses and remarkable layer integrity at early-stage.

Beyond 65FD-SOI, 28FD-SOI, 22FD-SOI production granted technologies, continuous SmartCutTM development support advanced SOI requirements. To improve SOI layer thickness variability, a 2nd generation chemical thinning process step is proposed. 11% and 25% improvements are demonstrated on 100% and on 75% of the wafer surface, respectively. This improved product is ready for pre-production.

To support 3D Sequential integration with a cost effective layer transfer, SmartCut process at low temperature (below 500°C) is proposed. Excellent SOI & BOX layers thickness uniformities with best in class SOI roughness are demonstrated, while layer integrity is already compliant with development grade requirements.

3D sequential integration is shown to be compatible with a back gate implementation suitable for dynamic V th tuning of the FDSOI top tier devices. The back gate is inserted seamlessly into the 3D sequential process flow during the top Si layer transfer, providing a close proximity to the top tier device, as well as a uniform and high quality thermal back oxide. A threshold voltage tuning of ~103mV/V and ~139mV/V is obtained in p-and nMOS top tier junction-less devices, respectively, over a back gate bias range of +/-2V. BTI reliability measurements show no detrimental impact of the back gate bias. Back-gating can therefore be used to enhance the $I_{ON}$ performance with no reliability penalty. The buried metal line is also shown to lower crosstalk by metal shielding insertion between top and bottom tier metal lines, with a reduction larger than 10dB up to 45GHz.

Sequential or monolithic 3D integration requires a combination of advanced manufacturing processes and highly reliable integration scheme at both device and substrate level. In order to achieve this, front-end layer transfer technology looks as key element of 3D integration flow. In this paper, we will bring an insight on technology challenges as well as solutions to enable sequential 3D device integration. We will also exhibit successful demonstration of low temperature device stacking using junctionless top devices.

Beyond 65FD-SOI, 28FD-SOI, and 22FD-SOI production granted technologies, SmartCut™ development supports both advanced FD-SOI and low temperature SOI roadmaps. Ultrathin SOI and BOX materials developments are reported, including 4-nm SOI and 15-nm BOX layers, with performances close to production-grade (SOI layer thickness variation at wafer and device scale, SOI layer defect density). To support 3-D sequential integration, layer transfer at low temperature (below 500 °C) with SmartCut is demonstrated, on the path to a cost effective option. Best in class—equivalent to Epi bulk—SOI layers thickness variability at device scale is demonstrated. Excellent SOI and BOX layers thickness uniformities at wafer level are also highlighted while layer integrity from surface to crystalline defect density point of view are already compliant with development grade requirements.

We report for the first time the implementation of SiGe buried stressors in the context of research and development of an advanced foundry FDSOI process and the observation of improved transconductance and current drive performance of n-channel FDSOI MOSFETs. Epitaxial SiGe stressors grown by CVD at Applied Materials were incorporated under the buried oxide of 300 mm FDSOI wafers by Soitec using lower temperature SOI bonding, splitting and thinning processes and the wafers were subsequently processed through an FDSOI development line at GLOBALFOUNDRIES. The use of FDSOI with buried stressor under the BOX eliminates the risk of extended defects in the epitaxial SiGe layer penetrating up into the SOI channel and also provides an opportunity to obtain a high level of strain in any semiconductor on insulator. A 70 nm thick SiGe buried stressor with 20% Ge is shown to provide a 10% improvement in Idsat at a fixed Ioff for n-FETs with 20 nm gate length and transconductance, gm is correspondingly improved by 15%.

Bulk silicon device technologies are reaching fundamental scaling limitations. The 28 nm and 22 nm technology nodes have seen the introduction of Ultra-Thin Body and Buried Oxide Fully Depleted SOI (UTBB-FDSOI) [1] and FinFETs [2], respectively. Fully Depleted transistor technologies are mandatory to suppress short channel effects. Today, all major research and development alliances carry the message that the silicon and its Fully Depleted transistor technologies have the potential to address roadmap requirements down to the 10 nm node. High mobility materials are expected to replace silicon as the channel material: attention has recently been focused on III-V (such as GaAs or InGaAs) and germanium (Ge). Ge has a privileged status: indeed, it belongs to column IV of Mendeleiev Table and it is a good candidate for high mobility p-channel and n-channel devices. Hole mobility (respectively electron mobility) in bulk Ge is indeed roughly 4 times (2 times) that in bulk Si. Nevertheless, changing from Si to Ge influences more than just the on-state current. The smaller bandgap value of Ge (0.66 eV versus 1.12 eV for Si) increases the junction leakage, and may therefore lead to a significant increase in the transistor off-state current [3-4]. SiGe alloy material with a high Ge ratio is a good compromise. Recently high-Ge-content (HGC) SiGeOI finFET have been demonstrated with record mobility values and good cut-off behavior [5] indicating the potential of such a channel material. In this paper, we will present our work on 300 mm SiGe-on-insulator (SiGe-OI) substrates with high Ge concentrations (70%). The process flow is illustrated in Fig.1. The standard SOI Smart CutTM process has been adapted for SiGe-OI substrates. The first focus is on the donor substrate and the SiGe epilayers. The donor surface quality should be carefully controlled and optimized before the bonding step. Fig. 2 shows the X-ray reflectivity measurements on the top layers of the Si0.3Ge0.7stack at the end of the epitaxial process steps. The significant interference fringes indicate the good quality of the different surfaces and interfaces which is confirmed by the roughness measurement (Atomic Force Microscopy image in Fig. 2 - right) with a Root Mean Square (RMS) roughness value as low as 0.18 nm on top of the donor substrates. The bonding process and the adapted Hydrogen-induced layer transfer inside the HGC SiGe layer will be presented. The second focus is on the finishing process steps to obtain the desired HGC SiGe-OI substrate. To ensure a good thickness control, the combination of multi-layer donor materials and selective chemical etching process has replaced the polishing removal process. As shown in Fig. 3, it enables to reach a SiGe-OI layer of 56 nm with a uniformity of +/- 3.5 nm at a 300 mm substrate scale. Final RMS surface roughness as low as 0.3 nm is obtained on finished HGC SiGe-OI substrate. Acknowledgment: The authors are grateful for the support given by the European Commission (ECSEL-WAYTOGO FAST 662175) [1] J. Hartmann, FDSOI workshop, 2012 [2] C. Auth, VLSI-T, 2012 [3] C. Claeys and E. Simoen, Eds., Germanium-based technologies – From materials to devices. Elsevier, 2007. [4] G. Eneman, ESSDERC 2007. [5] Hashemi, VLSI 2015. Figure 1

This paper reviews the properties of the SOI wafers fabricated using the Smart Cut™ technology, with ultra-thin body and buried oxide (BOX) required for the FD-SOI CMOS platform. It focuses on the parameters that require specific attention for this technology, namely, the top silicon layer thickness uniformity and buried oxide reliability. The first one is linked to the threshold voltage variability and the second to the active role played by the BOX when a back-bias is used. An overview of the specific process optimization and metrology developed to achieve the targeted specifications is given.

Fully depleted silicon-on-insulator (FD-SOI) semiconductor technology enables scalability of planar semiconductors devices with unique body-bias capability. FD-SOI technology offers best energy efficiency, highest performance of integrated RF and superior reliability ICs for IoT, automotive and mobile connectivity application.

Multiples technology nodes in production are now based on FD-SOI thin film substrates. The development of these substrates has required several technical innovations (SmartCut process adaptation, new metrology introduction), which are discussed in this paper.

300 mm ultrathin Silicon-On-Insulator (SOI) wafers with SiGe/Si stacks on top were used as pre-structures for the fabrication of 5 nm thick SiGe-On-Insulator (SGOI) substrates obtained by the Ge enrichment technique. Those substrates will be used as the channel of advanced Fully Depleted (FD) p-type Metal Oxide Semiconductor Field Effect Transistors (pMOSFET). We present in the first part the successful fabrication of 5 nm SGOI wafers. Various characterization techniques are used to investigate the Ge profile and the final strain in the fabricated 5 nm Si 0.7 Ge 0.3 film. Secondary Ions Mass Spectrometry (SIMS) and Scanning Transmission Electron Microscopy (STEM) clearly show that the Ge content is very homogeneous ( x Ge = 30 ± 1%) in the SiGe layer. Raman spectroscopy and High Angle Annular Dark Field (HAADF) STEM both confirm that the 5 nm thick SiGe film is compressively strained (−2 GPa). The second part is dedicated to the sensitivity of the Ge enrichment process (based on numerical modelling). We investigate the impact of single and combined fluctuations of the pre-structure parameters ( T Si , T SiGe,0 , x Ge,0 ) on the final SiGe layer ( T SiGe , x Ge ).

Devices using fully depleted undoped channels are among the most promising candidates for the next device generations due to their better immunity to short channel effects (SCE) (1) and to random dopant fluctuation. Channel engineering and control are then critical as silicon thickness fluctuation is a statistical source of VT variability and strained channels provide 47% increase in the drive current for NFETs (2) without any degradation for PFETs (3). SOI substrates from Soitec provide a complete set of manufacturing solutions either for planar or three-dimensional (FinFET) devices as they pre-integrate critical characteristics of the transistors within the wafer structure itself. Substrate robustness and readiness have been demonstrated. For planar devices the SOI thickness uniformity is controlled at +/-5A (6sigma value, all sites, all wafers) in high volume manufacturing mode. For three-dimensional devices, substrate requirements are extremely close to partially depleted ones which are in high volume manufacturing for more than 7 years.

SOI wafers have been used for digital applications for 2 decades. Historically separated between the high-performance, Partially Depleted (PDSOI) [1] and ultra-low power Fully Depleted (FDSOI) [2], the two architectures merged more recently into the UTBB-FDSOI (Ultra-Thin Body & BOX) technology [3]. In order to maintain optimum device performance, the buried oxide (BOX) thickness has been scaled from 25nm (28nm node) to 20nm (22nm node). In this paper we present the benefits of further scaling the BOX to 15nm for the next node and describe the process used to fabricate such SOI wafers along with their physical and electrical properties.

session B8L-E: Variability and Reliability in advanced MOSFETs; International audience; The Hot Carrier (HC) reliability of NMOS transistors fabricated on biaxially tensile-strain SOI substrates (sSOI) is compared to that of devices fabricated on standard unstrained SOI substrates. It is shown that sSOI-based devices not only exhibit a 10% higher performance in term of ION/IOFF but also show superior HC reliability at same drive current. This reliability improvement may be explained by a better interface quality for sSOI films.

SOI Buried Oxide (BOX) electrical quality is assessed through Charge to Breakdown, Breakdown Voltage, low field leakage, BOX fixed charge density and BOX/Si interface trap density measurements. Breakdown electrical field higher than 10 MV.cm−1 and 10 years lifetime at operating voltages in excess of 16V are reported on thin BOX layers.

session 2F: Process Integration; International audience; In this paper, we investigate the potential of strained Silicon-On-Insulator (sSOI) for the future advanced CMOS nodes. Strained FDSOI depicts a 30% higher performance in term of ION/IOFF thanks to higher mobility. Changes in band structure reduce the gate leakage and devices depict superior HC reliability at same drive current. The better interface quality with sSi layer leads to higher immunity to dangling bonds generation. Strain integration does not affect BTI and breakdown reliability.

Elastic relaxation after Fin formation in intrinsically-strained materials was presented. Reported simulations are correlated with NBD strain measurements and are consistent with length dependence of drain current in sSOI FinFETs. Stress in the Fin's channel region depends on Fin length and height. dingle layer structured Fins are much more resistant to elastic relaxation than dual layer structured Fins, due to overall structure height. On dual layer structure Fins, significant relaxation is expected for LFin shorter than 750nm, while single layer structured Fins do not relax significantly until 300nm. For transistor layout, elastic relaxation effects should be modeled or circumvented. Fin Length effects need to be added to other layout effects in Spice models.

Bulk silicon device technologies are reaching fundamental scaling limitations. The 28nm and 22nm technology nodes have seen the introduction of Ultra-Thin Body and Buried Oxide Fully Depleted SOI (UTBB-FDSOI) [1] and FinFETs [2], respectively. Fully Depleted transistor technologies are mandatory to suppress short channel effects. Today, all major research and development alliances carry the message that the silicon and its Fully Depleted transistor technologies have the potential to address roadmap requirements down to 10nm node. Innovations will be necessary for lowest node (under 10nm). Specifications are to continue to ensure a good electrostatic control while providing excellent electrical performance. To meet these demands, several research areas (substrate engineering as well as multiple gate devices and 3D integration) will be involved in integrated circuit fabrication (Fig. 1). High mobility materials are expected to replace silicon as the channel material: attention has been focused recently on the III-V and the Ge materials (Fig.1). Indeed, III-V semiconductors (such as GaAs, InP, InGaAs and InAs) have extremely high electron mobility and low electron effective mass and Ge has extremely high hole mobility and low hole effective mass [3]. In order to avoid short channel effects, these “new” materials have to be transferred as thin layers on buried oxide layers. SOI substrates are fabricated using the Smart CutTM technology. This process, based on hydrogen implantation and wafer bonding, made it possible to transfer a thin layer of crystalline material from a donor substrate to another substrate. This versatile technique for thin layer transfer enables the fabrication of hetero-substrates with a large choice for the crystalline superficial layers, the buried layers and even the handle substrates (Fig. 2). For More Moore applications, this leaves the freedom to transfer Ge or III-V thin layer on an optimized buried oxide layer. In this paper, we will present our latest work on advanced SOI substrates for sub-28nm technology node and on novel “on insulator” substrates for sub-10nm node. We developed GeOI (Fig. 3) and InGaAs-OI (Fig. 4) substrates in 300mm. It is otherwise possible, thanks to low temperature direct bonding, to combine 3D CMOS integration (thereby increasing transistor density) and high mobility channel devices : a monolithic and vertical co-integration of GeOI pMOSFETs stacked on SOI nMOSFETs [4] or a III-V-OI nMOSFETs stacked on a SiGeOI pMOSFETs [5] have already been demonstrated with functional inverters and SRAM cells. Acknowledgments: the authors acknowledge financial support from the European Commission via the FP7-COMPOSE3 and from the French Government's Investissement d'Avenir program (eXact projet). [1] J. Hartmann, FDSOI workshop, 2012 [2] C. Auth, VLSI-T, 2012 [3] S. Takagi, IEEE TED, 2008 [4] P. Batude, VLSI 2009 [5] T. Irisawa, VLSI, 2013.

International audience; This paper investigates the intrinsic reliability of ultra-thin buried oxides (UTBOX) integrated in the last generation of FDSOI wafers obtained by the Smart Cut™ technology. In term of breakdown reliability, these state-of-the-art UTBOX oxides exhibit comparable performances with thermally-grown SiO2 references. In “the worst case condition”, the voltage for a 10 years lifetime of 25 nm thick BOX, is estimated to 14 V, which largely exceeds the maximum operating conditions for back-bias [+3 V, –3 V] in advanced FDSOI integrated circuits. This makes UTBOX family of engineered substrates fully compatible and suitable for multi-VT applications.

Now that silicon product results are becoming available, and that the FD-SOI substrates hit the required uniformity to enable such products. It can now be said that Planar FDSOI is a credible manufacturing technology at 28nm. Furthermore, the technology is in place and has been proven to enable further scaling to at least the 10nm node.

We fabricated highly stressed FDSOI pMOSFETs down to 15nm gate length. The impact of different stressors (CESL, raised sources and drains, STI) is studied for different device geometries and channel orientations ( or ). We evidence that pMOSFETs along are more sensitive to stress: STI degrades narrow devices compared to wide ones whereas compressive CESL (−3GPa) and SiGe S/D improve performances (+133% mobility, +16% I ON on 10μm wide devices). This makes the orientation the most favorable channel orientation for strained pMOSFETs on planar FDSOI.

The transition to fully-depleted (FD) transistor technology is taking place today, either towards planar architectures on SOI wafers [1] or towards 3D-like architectures (FinFET or Trigate) [2]. The reason for this change is better electrostatic control, and reduction or even complete elimination of random dopant fluctuations, leading to much improved Vt variability.

For the first time, CMOS devices on UTBOX 25nm combined with strained SOI (sSOI) substrates have been demonstrated. A 20% Ion boost is highlighted with these substrates compared to the standard UTBB SOI ones. Performance up to 1530µA/µm @ Ioff=100nA/µm (Vd 1V) for a nominal Lg=30nm with a CET of 1.5nm for the NMOS has been achieved. The viability of this substrate has been demonstrated thanks to our hybrid process, through threshold voltage modulation and leakage current reduction, with back biasing for short devices. In addition, cell current improvement of 23% in 0.12µm2 bitcell is noticed for sSOI at the same stand-by current vs the standard UTBB SOI. Finally, the functionality of hybrid ESD device underneath the BOX is demonstrated.

High-performance strain-engineered ETSOI devices are reported. Three methods to boost the performance, namely contact strain, strained SOI (SSDOI) for NFET, and SiGe-on-insulator (SGOI) for PFET are examined. Significant performance boost is demonstrated with competitive drive currents of 1.65mA/µm and 1.25mA/µm, and I eff of 0.95mA/µm and 0.70mA/µm at I off =100nA/µm and V DD of 1V, for NFET and PFET, respectively.

Smart Cut™ technology is used to manufacture Strained-SOI (sSOI) substrates. These substrates are proposed to boost performance for both planar and FinFET Fully Depleted SOI devices. To comply with tight transistor variability requirements, strong emphasis has been put on layer thickness control and low stress variation. A 1.2 A RMS roughness and less than 10% stress fluctuation are already demonstrated for sSOI wafers.

This paper will explain the challenges and solutions for ultra thin SOI inspection using a laser light scattering based system. The impact of reflectivity on haze, sizing and minimum threshold will be detailed. We will show how the required sensitivity for 28nm (and beyond node) SOI inspection was achieved using a commercially available unpatterned DUV inspection system. We will also study improvements in defect classification.

Recent UTBB device data at sub-25nm gate length demonstrate good performance, small V T variation and excellent low power operation. In addition, very uniform Soitec Xtreme SOI™ product substrates are now available and compliant with device requirements. Thus the level of maturity of UTBB devices and substrates makes it possible for introduction at 20nm node. Multiple options at the substrate level to further boost the performance open up the path to improve performance for future nodes.

Thickness uniformity of the Ultra Thin SOI (UTSOI) substrates is one of the key criteria to control Vt variation of the planar FDSOI devices. We present an evolutionary approach to SmartCutTM technology which already allows achieving a maximum total SOI layer thickness variation of less than ± 10 A on preproduction volume. Total thickness variation of ± 5 A is targeted.