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This research has developed a fabricating process of thin‐strain sensor by utilizing wafer‐level‐packaging (WLP) techniques. The thickness of sensor makes thinner, its performance is able to highly increase. However, the thinner sensor was fragile, and so it was difficult to handle in post processes. Thus, a thin sensor with lid by utilizing WLP techniques, which is tough to break even when handled, is proposed in this research. More than 250‐µm‐deep grooves were fabricated around the lid by deep reactive ion etching. After the lid substrate was bonded on the sensor substrate with a resin, the sensor and lid substrates were respectively polished to 50 and 200 µm thickness. The lids were released along the grooves, and the 50‐µm‐thick strain sensors were able to be fabricated by utilizing WLP techniques. This sensor was used as a diaphragm to measure pressure. The sensors were assembled on a stainless steel housing without breakage. The performance of the developed sensor was almost showed with a conventional pressure sensor. [ABSTRACT FROM AUTHOR]

The slide-film damping effect caused by cavity structures is easily neglected in the design of bulk-micro-machined resonant MEMS device fabrication and packaging processes. On the basis of theory calculations, simulations, and actual tests, in this study, we investigate the cavity-depth effect on 3D wafer-level packaged MEMS resonators with the in-plane-motion mode, in which slide-film damping is dominant. On the one hand, it is found that the slide-film damping coefficient is inversely proportional to the cavity depth and remains stable for the cavity depth above a specific value. The critical cavity depth acquired from theoretical results is ~10 µm, which is distinct from that of ~30 µm from simulation results. On the other hand, the variation tendency of simulation results is more in agreement with those of test results for fabricated devices than the theoretical prediction. Hence, before the structure fabrication for a resonator dominated by slide-film damping, it is imperative to choose a conservative cavity depth with a relatively high value from the combination of theory and simulation analyses, so as to ensure the high or desired Q-factors of fabricated resonators, particularly in wafer-level packaging with the low-vacuum or atmospheric pressure. Overall, this work provides not only an analysis strategy on device cavities' slide-film damping but also the optimization design of wafer-level packaging structures and processes. [ABSTRACT FROM AUTHOR]

Most microsensors are composed of devices and covers. Due to the complicated structure of the cover and various other requirements, it difficult to use wafer-level packaging with such microsensors. In particular, for monolithic microsensors combined with read-out ICs, the available process margins are further reduced due to the thermal and mechanical effects applied to IC wafers during the packaging process. This research proposes a low-temperature, wafer-level vacuum packaging technology based on Cu-Sn bonding and nano-multilayer getter materials for use with microbolometers. In Cu-Sn bonding, the Cu/Cu3Sn/Cu microstructure required to ensure reliability can be obtained by optimizing the bonding temperature, pressure, and time. The Zr-Ti-Ru based nanomultilayer getter coating inside the cap wafer with high step height has been improved by self-aligned shadow masking. The device pad, composed of bonded wafer, was opened by wafer grinding, and the thermoelectrical properties were evaluated at the wafer-level. The bonding strength and vacuum level were characterized by a shear test and thermoelectrical test using microbolometer test pixels. The vacuum level of the packaged samples showed very narrow distribution near 50 mTorr. This wafer-level packaging platform could be very useful for sensor development whereby high reliability and excellent mechanical/optical performance are both required. Due to its reliability and the low material cost and bonding temperature, this wafer-based packaging approach is suitable for commercial applications. [ABSTRACT FROM AUTHOR]

In this paper, we present wafer-level packaging technology for surface acoustic wave (SAW) filters with higher long-term reliability and better electrical performance. This article focuses on the package structure, fabrication processes, and reliability for the SAW filter wafer-level package (WLP). The key processes, including cavity wall (CW) dam formation through non-photosensitive film vias development using a laser drilling process, a redistribution layer (RDL), and ball-grid array formation are developed. In addition, a numerical study based on the finite element model has been conducted to analyze the stress distribution of Cu RDL traces. In addition, the CW dam and the roof layer are covered with polymer, which solves the delamination problem between the CW dam and the substrate. Meanwhile, after practical verification, the SAW filter WLP was resistant to encapsulating pressure using a high elastic modulus capping material, which solved the collapse problem. Additionally, a comparison of the RF filter package's electrical performance following the preconditional level 3 and unbiased highly accelerated stress test revealed no differences in insertion attenuation across the passband (<0.2 dB, standard value: 1 dB). The final packages passed the reliability tests in the field of consumer electronics. [ABSTRACT FROM AUTHOR]

Packaging radio-frequency microelectromechanical systems (RF-MEMS) is mandatory for their integration in electronic systems. This paper discusses the integration of a Au−Ru/AlCu contact in a MEMS fabrication process with a wafer-level packaging (WLP) step through Al−Ge eutectic bonding. The Au contact is embedded in a movable fixed−fixed beam made of $30 ~ \mu \text{m}$ thick Si while Ru is used as a coating metal on top of the AlCu static electrode. The measured return loss and isolation of the contact, up to 40 GHz, are $\geq -1.7$ and $\leq -12$ dB respectively. The WLP Au−Ru/AlCu contact has an electrical resistance $\leq 1.2 ~ \Omega $ up to 3 million cycles in hot switching at 0.1 W before failing due to high electrical resistance. Au hillocking is identified as the only intrinsic limiting mechanism that can be mitigated by an appropriate design rule. It is demonstrated that Au−Ru/AlCu is a promising contact configuration, compatible with Al−Ge eutectic bonding, and can be integrated in a standard MEMS fabrication process flow for the development of a robust generation of WLP RF-MEMS. [ABSTRACT FROM AUTHOR]

We explore compatibility of Ru with Al-Ge eutectic wafer bonding. We first present experiments to check for the presence of Ru ternary alloy poisoning inhibiting Al-Ge melting as well as evaluations of Al-Ge melt wettability on Ru and diffusion outcomes following bond-simulating anneals. Results show that Ru is stable with no observed microstructural changes or dissolution in the melt, indicating no ternary poisoning for the applied thermal budget. Ru was found to act as an effective barrier offering good melt wettability in all considered configurations with Al and Ge. From inspection of the binary constituents of Al-Ge-Ru we propose that Al-Ge eutectic melting temperature will decrease marginally for Ru contamination in a 1-2% range before a drastic increase in melting temperature (>10°C/% Ru) at higher Ru compositions. We then demonstrate wafer-level packaged 200 mm devices and MEMS with strong bond outcomes of devices bearing Ru contacts. We conclude that Ru has high compatibility with Al-Ge eutectic bonding. [2022-0037] [ABSTRACT FROM AUTHOR]

This paper reports an approach for co-fabrication of silicon-on-insulator (SOI) sensors with low-resistance vertical electrical interconnects in thick (up to 600μm ) wafers. The thru-wafer interconnects double-sided (TWIDS) process is based on bottom-up seedless copper electroplating, and allows for voids-free features and high aspect ratio (wafer thickness to copper diameter ratio of 10:1). This work describes the design trade-offs, process flow, and characterization of interconnects. TWIDS technology is compatible with a standard SOI micro-electro-mechanical systems (MEMS) fabrication process and is applicable for micro sensors, such as accelerometers, gyroscopes, resonators, and RF MEMS devices, as well as for the 3-D MEMS assemblies. As a demonstration of potential applications, miniature toroidal ring gyroscopes were fabricated using the TWIDS process. The experimental characterization showed that the low-resistance interconnects with low parasitic losses are suitable for integration with capacitive-detection sensors. In addition, the mechanical stability of the interconnects is discussed in this paper, and a method to enhance structural rigidity by means of filling the insulating gaps with Parylene C is demonstrated. [2017-0179]

Chip-scale atomic clocks (CSACs) have been extensively investigated and many prototypes or products have been realized as time sensors. Researchers focus on improving the frequency stability performance, reducing the volume and the power consumption of CSACs. To the best of our knowledge, the physics packages reported until now are all assembled from discrete components. This traditional assembly method has a very low efficiency and causes variations among different physics packages. In this article, we propose a wafer-level assembled physics package for CSACs based on three dimensional (3-D) wafer-level packaging (WLP) and microelectromechanical system (MEMS) technologies. The components of the physics package are all fabricated on wafers. These wafers are integrated together vertically and then diced into separate physics packages. The proposed method has the advantages of high uniformity among different physics packages and high efficiency. And it improves the utilization rate of wafers by reducing the unused area. Thus, the production cost is reduced considerably. The volume of the proposed functional physics package is less than 8 mm3. The prototype chip-scale atomic clock incorporating the proposed physics package reveals the coherent population trapping (CPT) linewidth of 1.8 kHz and the total power consumption of about 20mW. The frequency stability is about $6.1 \times 10^{-12}$ @1000s. The observed results demonstrate promising performance of the wafer-level assembled physics package. The approach described in this article reveals a viable method for batch production for its low cost, high efficiency and high product uniformity. [ABSTRACT FROM AUTHOR]

Most microsensors are composed of devices and covers. Due to the complicated structure of the cover and various other requirements, it difficult to use wafer-level packaging with such microsensors. In particular, for monolithic microsensors combined with read-out ICs, the available process margins are further reduced due to the thermal and mechanical effects applied to IC wafers during the packaging process. This research proposes a low-temperature, wafer-level vacuum packaging technology based on Cu-Sn bonding and nano-multilayer getter materials for use with microbolometers. In Cu-Sn bonding, the Cu/Cu3Sn/Cu microstructure required to ensure reliability can be obtained by optimizing the bonding temperature, pressure, and time. The Zr-Ti-Ru based nanomultilayer getter coating inside the cap wafer with high step height has been improved by self-aligned shadow masking. The device pad, composed of bonded wafer, was opened by wafer grinding, and the thermoelectrical properties were evaluated at the wafer-level. The bonding strength and vacuum level were characterized by a shear test and thermoelectrical test using microbolometer test pixels. The vacuum level of the packaged samples showed very narrow distribution near 50 mTorr. This wafer-level packaging platform could be very useful for sensor development whereby high reliability and excellent mechanical/optical performance are both required. Due to its reliability and the low material cost and bonding temperature, this wafer-based packaging approach is suitable for commercial applications.

Through-silicon via (TSV) is a key packaging technology that facilitates the 2.5D/3D integration of microelectromechanical system (MEMS) devices. Among various MEMS technologies, C-MEMS enables micro/nanoscale 3D carbon structure manufacturing using high-temperature (600–1200 °C) pyrolysis. These high-temperature conditions limit the application of conventional TSV technologies to C-MEMS devices. This study presents a novel TSV with carbon via-sealing plates that are adaptable to C-MEMS device packaging. Via holes are drilled before integrating the MEMS device to protect the delicate micro/nanoscale structures. Moreover, the topside via inlet is sealed with a thin conductive pyrolyzed carbon plate to prevent the contamination of the via interior during the C-MEMS process and ensure an electrical connection between the devices and the vias. After integrating the C-MEMS devices, TSV fabrication is completed by coating the via inside with a metal layer from the wafer's bottom side, achieving a conductance per unit area of approximately 327 S/mm2 (via diameter = 33 μm, length = 100 μm). The applicability of the proposed wafer-level TSV technology to C-MEMS devices is then verified through the implementation of a suspended carbon nanowire-based gas sensor integrated with the developed TSV, which exhibits excellent signal transmission. Furthermore, the proposed TSV packaging technology can be applied to various micro/nanofabrication technologies because of its high-temperature/wet-process compatibility and cost-effective fabrication. [Display omitted] • Novel high-temperature adaptive TSV technology with pyrolyzed carbon sealing plates. • Via holes are pre-drilled to protect delicate micro/nanoscale carbon devices. • Topside via inlet is sealed with a thin conductive pyrolyzed carbon plate. • The unique sealing plate is achieved by pyrolyzing freestanding photoresist film. • The proposed TSV has been verified using a carbon nanowire-based gas sensor. [ABSTRACT FROM AUTHOR]

In this paper, we present wafer-level packaging technology for surface acoustic wave (SAW) filters with higher long-term reliability and better electrical performance. This article focuses on the package structure, fabrication processes, and reliability for the SAW filter wafer-level package (WLP). The key processes, including cavity wall (CW) dam formation through non-photosensitive film vias development using a laser drilling process, a redistribution layer (RDL), and ball-grid array formation are developed. In addition, a numerical study based on the finite element model has been conducted to analyze the stress distribution of Cu RDL traces. In addition, the CW dam and the roof layer are covered with polymer, which solves the delamination problem between the CW dam and the substrate. Meanwhile, after practical verification, the SAW filter WLP was resistant to encapsulating pressure using a high elastic modulus capping material, which solved the collapse problem. Additionally, a comparison of the RF filter package’s electrical performance following the preconditional level 3 and unbiased highly accelerated stress test revealed no differences in insertion attenuation across the passband (

This paper reports a deep‐ultraviolet LED (deep‐UV‐LED) package based on silicon MEMS process technology (Si‐PKG). The package consists of a cavity formed by silicon crystalline anisotropic etching, through‐silicon vias (TSVs) filled with electroplated Cu, bonding metals made of electroplated Ni/AuSn and a quartz lid for hermetic sealing. A deep‐UV LED die is directly mounted in the Si‐PKG by AuSn eutectic bonding without a submount. It has advantages in terms of size, heat dissipation, light utilization efficiency, productivity and cost over conventional AlN ceramic packages. We confirmed a light output of 30 mW and effective reflection on Si (111) cavity slopes in the Si‐PKG. Based on simulation, further improvement of the optical output is expected by optimizing DUV‐LED die mount condition. [ABSTRACT FROM AUTHOR]

Silicon migration seal (SMS) wafer‐level packaging is proposed for high vacuum encapsulation of MEMS. The sealing of vent holes is possible based on silicon surface migration effect at 1100°C in 100% hydrogen ambient without deposition, if the size of the vent holes is properly designed. The feasibility of SMS packaging was experimentally demonstrated using 4‐inch wafers. Hermetic sealing was confirmed after 168 hours from the packaging process by diaphragm displacement in the cap wafer. [ABSTRACT FROM AUTHOR]

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The sensor technology and the packaging method influence drastically the device performance by conditioning its sensitivity, the operating conditions and the distance between the magnetic source and the sensor. Magnetic encoders based on magnetoresistive (MR) sensors standout as a technology immune to dust, oil and fluids, and a cheaper system than optical solutions. Furthermore, they provide a higher spatial resolution, sensitivity and bandwidth than Hall effect sensors. However, to achieve a competitive prototype for applications with high constraints, it is necessary to combine state-of-the-art MR sensors with a packaging solution that entails a minimum impact on the sensor performance. Therefore, a new packaging method developed at wafer level is proposed for motion and positioning systems in planar architectures. The final prototype consists on a hybrid rigid-flexible MR probe combining a sensing chip with a flexible polyimide (PI) connector. This packaging technique pushes the contacts and establish electrical contact with the outer electronics on the back side or at a lower level parallel to the sensor plane, achieving a minimum distance of $7.5~\mu \text{m}$ between the sensor and the magnetic source. Finally, the device was successfully implemented as a magnetic encoder on a linear magnetic scale with $80~\mu \text{m}$ bit length revealing a sin/cos like signal with an amplitude of 42 mV $_{\mathrm {RMS}}$ at a reading distance of $80~\mu \text{m}$. [ABSTRACT FROM AUTHOR]

A wafer‐level packaging (WLP) technology for millimeter‐wave power devices is presented, which features simple fabrication, low‐signal transition loss, and thermal consideration. Instead of using a rigid interposer, the proposed WLP technology incorporates thick copper sheet and an adhesive tape as the initial carrier. Short electroplated interconnection showed transition loss within 0.2 dB and return loss above 20 dB, at frequency range up to 30 GHz. We demonstrate the WLP with an RF power amplifier at 28 GHz. The power‐added efficiency (PAE) of the power amplifier packaged in the proposed technology is 30% at an output power of 27.5 dBm, which is identical to an unpackaged integrated circuit (IC) wire bonded on a printed circuit board. The size of the IC, and the final packaged sample was 2.2 × 1.5 × 0.1 mm3 and 3.3 × 2.4 × 0.2 mm3, respectively. [ABSTRACT FROM AUTHOR]

This paper presents a novel wafer-level packaging method for shunt, capacitive RF MEMS switches using BCB as the adhesive interlayer. Fabrication and electrical characteristics of the proposed package were initially evaluated for 50 $\Omega $ CPW lines. Microwave measurements of these packaged test structures were fitted to a circuit model, which was later employed to optimize the package for RF MEMS switches. The proposed packaging method was next successfully integrated with an in-house RF MEMS fabrication process. Mechanical and microwave characteristics of these switches were investigated prior to and following the packaging process. Measured shear strength for five packaged switches averages to 18.3 MPa. MEMS bridges deflect by 71 nm on the average due to the packaging step. C-V measurements show 4.2 V average increase in pull-in voltages. Millimeter-wave measurements confirm the negligible effect of package on switch performance. Measured upstate return and insertion losses at 35 GHz read 28 and 0.4 dB, respectively. The downstate isolation attains 35 dB at 35 GHz for most of the packaged switches. Lifetime measurements of a packaged switch demonstrate 10.2 billion cycles without failure. [2018-0268] [ABSTRACT FROM AUTHOR]

Perspective view of the vacuum-packaged micromirror. • The design, fabrication, and wafer-level packaging of an electromagnetic biaxial scanning micromirror is presented. • The vacuum packaging was implemented by anodically bonding the glass cap wafer to both sides of the micromirror. • The quality factor of the packaged mirror is 1923 for the horizontal scan, whereas that of the device in the air is 649.6. • The estimated vacuum level of the package is 1.65 ± 0.85 Torr. We herein present the design, fabrication, and wafer-level packaging of an electromagnetic biaxial scanning micromirror. The vacuum packaging of the micromirror was implemented by anodically bonding the glass cap wafer to both sides of the silicon substrate with the micromirror. The measured quality factor of the vacuum packaged micromirror is 1923.2 for the horizontal scan, whereas that of the device in the air is 649.6. The maximum optical scan angle of the vacuum packaged micromirror is 24.19° at 155 mApp and 11.9 kHz for the horizontal scan, and 7.1° at 204.7 mApp and 60 Hz for the vertical scan. The estimated vacuum level of the package is 1.65 ± 0.85 Torr. [ABSTRACT FROM AUTHOR]

Au–Au‐bonding‐based wafer‐level vacuum packaging technology using in‐plane feedthrough of thick Au signal lines was developed for high‐frequency micro electromechanical system (RF MEMS). Compared with conventional technology based on glass frit bonding, the developed technology is advantageous in terms of smaller width of sealing frames, lower process temperature, and smaller amount of degas. To guarantee the hermetic sealing, the adhesion between the thick Au lines and a SiOx dielectric frame is improved by an Al2O3 interlayer by atomic layer deposition. The steps of the dielectric frame above the thick Au lines are absorbed by an electroplated Au seal ring planarized by fly cutting. The thermocompression bonding of the Au seal rings of 20‐100 μm width was done at 300 ºC. A cavity pressure of about 500 Pa or lower was measured by "zero balance method" using Si diaphragms. Vacuum sealing was maintained for more than 19 months, and the leak rate is less than 8×10‐16 Pa m3/s. The isolation of open signal lines was measured up to 10 GHz for different designs of the sealing ring and SiOx dielectric frame. The influence of the in‐plane feed through to the isolation is as low as 2‐3 dB, if the width of the sealing ring is 20 μm and the thickness of SiOx dielectric frame is larger than 10 μm. The developed wafer‐level packaging technology is ready for applications to an radio frequency (RF) MEMS switch. [ABSTRACT FROM AUTHOR]

The next generation of satellites will need to tackle tomorrow's challenges for communication, navigation and observation. In order to do so, it is expected that the amount of satellites in orbit will keep increasing, form smart constellations and miniaturize individual satellites to make access to space cost effective. To enable this next generation of activities in space, it is vital to ensure the ability of these satellites to properly navigate themselves. This control starts with attitude measurement by the dedicated sensors on the satellite, commonly performed by sun position sensors. The state-of-the art is confronted by large signal distortions caused by light reflected by the Earth's albedo as well as keeping up with the satellite miniaturization trend. This work aims to address both these issues, by presenting a microfabricated albedo insensitive sun position sensor in silicon carbide with wafer-level integrated optics. The presented 10 mm × 10 mm × 1 mm system reaches a mean angular accuracy of 5.7° in a ± 37° field-of-view and integrates an on-chip temperature sensor with a -3.9 mV K−1 sensitivity in the 20 °C to 200 °C range. [Display omitted] • First sun position sensor in silicon carbide technology with integrated 3D optics. • Thermocompressive wafer-level bonding and heterogeneous integration of the optics. • Device performance reaches mean angular accuracy of 5.7°in a ±37°field-of-view. • On-chip temperature sensor with -3.9 mV K-1 sensitivity in the 20–200 °C range. • Validated device operation up to 200 °C for harsh environment application. [ABSTRACT FROM AUTHOR]

In this paper, a co-design method and a wafer-level packaging technique of a flexible antenna and a CMOS rectifier chip for use in a small-sized implantable system on the brain surface are proposed. The proposed co-design method optimizes the system architecture, and can help avoid the use of external matching components, resulting in the realization of a small-size system. In addition, the technique employed to assemble a silicon large-scale integration (LSI) chip on the very thin parylene film (5 μm) enables the integration of the rectifier circuits and the flexible antenna (rectenna). In the demonstration of wireless power transmission (WPT), the fabricated flexible rectenna achieved a maximum efficiency of 0.497% with a distance of 3 cm between antennas. In addition, WPT with radio waves allows a misalignment of 185% against antenna size, implying that the misalignment has a less effect on the WPT characteristics compared with electromagnetic induction.

This paper presents a wafer-level vacuum-packaged z-axis capacitive micro accelerometer fabricated on a flexible polyimide substrate and encapsulated by another polyimide superstrate enabling the flexibility, bendability, and portability of both the device and the package. The novel low-cost and low-temperature encapsulation procedure requires a fewer fabrication steps than the processes, where a thin epitaxial Si layer or a full Si wafer with cavity is used as a superstrate. It also provides a better pliability. The fabricated micro accelerometers demonstrated excellent integrity when bowed down to 2-cm radius of curvature with the sensitivity varying between 139 and 174 fF/g, depending on the design, under the application of ±4 g of acceleration. The resonant frequencies varied from 800 Hz for the largest device to 1050 Hz for the smallest device. The results reported here represent the best performing, wafer-level-packaged flexible micro accelerometers to date. [ABSTRACT FROM AUTHOR]

Micro-electromechanical systems (MEMS) have been developed for sensors and other systems since 1971 at Tohoku University. Ion-sensitive FET (ISFET) probes made by micromachining were commercialized for pH and PCO2 catheters. Special attention was paid to packaging and wafer-level packaging based on glass-to-Si anodic bonding was applied for integrated capacitive pressure sensors, capacitive diaphragm vacuum gauges, MEMS switches, and other devices. Process equipment for not only MEMS but also integrated circuits (ICs) has been made in house because it is important for flexible prototyping and fabrication of novel devices. Equipment for deep reactive ion etching (RIE) of Si was developed and applied for an electrostatically levitated rotational gyroscope and other devices. Heterogeneous integration as MEMS on LSI has been made possible by the transfer of MEMS on a carrier wafer to an LSI wafer or by stacking a MEMS wafer on an LSI wafer using electrical interconnection with a through Si via (TSV). A piezoelectric MEMS switch on an LSI chip, surface acoustic wave (SAW) filters on an LSI chip, a tactile sensor network, and an active matrix electron emitter array are shown as examples of these technologies. [ABSTRACT FROM AUTHOR]

A radio-frequency micro-electro-mechanical system (RF MEMS) wafer-level packaging (WLP) method using pre-patterned benzo-cyclo-butene (BCB) polymers with a high-resistivity silicon cap is proposed to achieve high bonding quality and excellent RF performance. In this process, the BCB polymer was pre-defined to form the sealing ring and bonding layer by the spin-coating and patterning of photosensitive BCB before the cavity formation. During anisotropic wet etching of the silicon wafer to generate the housing cavity, the BCB sealing ring was protected by a sputtered Cr/Au (chromium/gold) layer. The average measured thickness of the BCB layer was 5.9 μm. In contrast to the conventional methods of spin-coating BCB after fabricating cavities, the pre-patterned BCB method presented BCB bonding layers with better quality on severe topography surfaces in terms of increased uniformity of thickness and better surface flatness. The observation of the bonded layer showed that no void or gap formed on the protruding coplanar waveguide (CPW) lines. A shear strength test was experimentally implemented as a function of the BCB widths in the range of 100-400 μm. The average shear strength of the packaged device was higher than 21.58 MPa. A RF MEMS switch was successfully packaged using this process with a negligible impact on the microwave characteristics and a significant improvement in the lifetime from below 10 million to over 1 billion. The measured insertion loss of the packaged RF MEMS switch was 0.779 dB and the insertion loss deterioration caused by the package structure was less than 0.2 dB at 30 GHz. [ABSTRACT FROM AUTHOR]

This paper reports on the design, fabrication, and characterization of wafer-level-packaged wide-bandwidth capacitive accelerometers with high aspect-ratio nanometer scale gaps utilizing sloped electrode configuration. Narrow gaps defined by the thickness of a sacrificial layer provide an increased electromechanical coupling that enables designing sensors with high operational bandwidth (~15 kHz), while maintaining low-noise performance. Furthermore, by sloping the sense fingers, one can get a larger traveling range for the proof mass than the thickness of the sacrificial layer, allowing for the realization of shock stops without additional fabrication steps. The proposed scheme was incorporated into a 1 mm \times1 mm accelerometer design with 270-nm gap and fabricated on a 40- \mu \text{m} -thick silicon-on-insulator wafer using an high-aspect-ratio combined poly and single-crystal silicon (HARPSS) process, and subsequently wafer-level-packaged at a reduced pressure level of ~10 torr. The damping factor of the device was tailored using dedicated damping electrodes to ensure stable operation of the quasi-static accelerometer at low-pressure. The noise density is measured to be 221~\mu \text{g}/\surd $ Hz at 1 Hz, exhibiting a bias instability of 178~\mu \text{g} , with a scale factor nonlinearity of less than ±0.4% in a full-scale range of ±16 g, and showing an operational bandwidth greater than 8.5 kHz. Furthermore, a number of fabricated sensors were dropped from 1.8 m height to apply shock acceleration levels greater than 1000 g; all of the prototypes remain operational to their specifications after the free-fall test. [2017-0137] [ABSTRACT FROM AUTHOR]

Au/Si eutectic bonding is considered to BE a promising technology for creating 3D structures and hermetic packaging in micro-electro-mechanical system (MEMS) devices. However, it suffers from the problems of a non-uniform bonding interface and complex processes for the interconnection of metal wires. This paper presents a novel Au/Si eutectic wafer bonding structure and an implementation method for MEMS accelerometer packaging. The related processing parameters influencing the Au/Si eutectic bonding quality were widely investigated. It was found that a high temperature of 400 °C with a low heating/cooling rate of 5 °C/min is crucial for successful Au/Si eutectic bonding. High contact force is beneficial for bonding uniformity, but the bonding strength and bonding yield decrease when the contact force increases from 3000 to 5000 N due to the metal squeezing out of the interface. The application of TiW as an adhesion layer on a glass substrate, compared with a commonly used Cr or Ti layer, significantly improves the bonding quality. The bonding strength is higher than 50 MPa, and the bonding yield is above 90% for the presented Au/Si eutectic bonding. Furthermore, the wafer-level vacuum packaging of the MEMS accelerometer was achieved based on Au/Si eutectic bonding and anodic bonding with one process. Testing results show a nonlinearity of 0.91% and a sensitivity of 1.06 V/g for the MEMS accelerometer. This Au/Si eutectic bonding process can be applied to the development of reliable, low-temperature, low-cost fabrication and hermetic packaging for MEMS devices. [ABSTRACT FROM AUTHOR]

We present the design and development of breath-mode silicon ring resonators fabricated using a commercial pure-play microfabrication process that provides ultraclean wafer-level vacuum-encapsulation. The micromechanical resonators are fabricated in MEMS integrated design for inertial sensors process that is developed by Teledyne DALSA Semiconductor Inc. The ring resonators are designed to operate with a relatively low DC polarization voltage, starting at 5 V, while providing a high frequency-quality factor product. We study the quality of the vacuum packaging using an automated testing setup over an extended time period. We study the effect of motional resistance on the performance of MEMS resonators. The fabricated devices had a resonant frequency of 10 MHz with the quality factor exceeding 8.4 × 104. [ABSTRACT FROM AUTHOR]