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In this work, we present a new defect localization capability on wafer-level chip-scale packages with small-scale Cu pillars using advanced 3D X-ray microscopy. In comparison with conventional microcomputed tomography (micro-CT) flat-panel technology, the synchrotron-based optically enhanced 3D X-ray microscopy can detect very small defects with submicron resolutions. Three case studies on actual failures (one from the assembly process and two from reliability testing) will be discussed to demonstrate this powerful defect localization technique. Using the tool has helped speed up the failure analysis process by locating the defects nondestructively in a matter of hours instead of days or weeks as needed with destructive physical failure analysis. [ABSTRACT FROM AUTHOR]

Cu pillars serve as interconnecting structures for 3D chip stacking in heterogeneous integration, whose height uniformity directly impacts chip yield. Compared to typical methods such as white-light interferometry and confocal microscopy for measuring Cu pillars, microscopic fringe projection profilometry (MFPP) offers obvious advantages in throughput, which has great application value in on-line bump height measurement in wafer-level packages. However, Cu pillars with large curvature and smooth surfaces pose challenges for signal detection. To enable the MFPP system to measure both the top region of the Cu pillar and the substrate, which are necessary for bump height measurement, we utilized rigorous surface scattering theory to solve the bidirectional reflective distribution function of the Cu pillar surface. Subsequently, leveraging the scattering distribution properties, we propose a hybrid bright-dark-field MFPP system concept capable of detecting weakly scattered signals from the top of the Cu pillar and reflected signals from the substrate. Experimental results demonstrate that the proposed MFPP system can measure the height of Cu pillars with an effective field of view of 15.2 mm × 8.9 mm and a maximum measurement error of less than 0.65 μm. [ABSTRACT FROM AUTHOR]

This paper introduces a cost-effective, high-performance approach to achieving wafer level vacuum packaging (WLVP) for MEMS-based uncooled infrared sensors. Reliable and hermetic packages for MEMS devices are achieved using a cap wafer that is formed using two silicon wafers, where one wafer has precise grating/moth-eye structures on both sides of a double-sided polished wafer for improved transmission of over 80% in the long-wave infrared (LWIR) wavelength region without the need for an AR coating, while the other wafer is used to form a cavity. The two wafers are bonded using Au-In transient liquid phase (TLP) bonding at low temperature to form the cap wafer, which is then bondelectrical and Electronics d to the sensor wafer using glass frit bonding at high temperature to activate the getter inside the cavity region. The bond quality is assessed using three methods, including He-leak tests, cap deflection, and Pirani vacuum gauges. Hermeticity is confirmed through He-leak tests according to MIL-STD 883, yielding values as low as 0.1 × 10−9 atm·cc/s. The average shear strength is measured as 23.38 MPa. The package pressure varies from 133–533 Pa without the getter usage to as low as 0.13 Pa with the getter usage. [ABSTRACT FROM AUTHOR]

Defective chips in wafer bin maps (WBMs) form different spatial patterns depending on the root causes of process failures. Therefore, the identification of defect patterns in WBMs can help practitioners identify the root causes. Previous studies have focused on wafer-level classification even though chip-level classification can provide additional information regarding defect locations and defect sizes. Chip-level classification is more challenging than wafer-level classification because existing chip-level classification methods require chip-level labels, which are laborious to collect. We propose a method for chip-level defect classification using only wafer-level labels based on weakly supervised semantic segmentation. We first train a classification network using wafer-level labels and extract class activation maps (CAMs), which are visualizations of the discriminative regions. We then generate chip-level pseudo-labels using the extracted CAMs and use these labels to train a segmentation network, which predicts chip-level defect types. Experimental results verify the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

Electrostatic discharge (ESD) failure is a major reliability problem for all forms of microelectronics products. ESD protection is required for all integrated circuits (ICs). As dimension scaling-down approaches its physical limit, heterogeneous integration (HI) emerges as a main pathway towards the age beyond Moore's Law to facilitate advanced microsystem chips with extreme performance and rich functionalities. Advanced packaging is a key requirement for HI-enabled integrated systems-on-chiplets (SoIC) that require robust ESD protection solutions. This article outlines key emerging technical challenges associated with smart future SoIC microsystem superchips in the context of advanced packaging technologies. [ABSTRACT FROM AUTHOR]

This research has developed a fabricating process of thin‐strain sensor by utilizing wafer‐level‐packaging (WLP) techniques. The thickness of sensor makes thinner, its performance is able to highly increase. However, the thinner sensor was fragile, and so it was difficult to handle in post processes. Thus, a thin sensor with lid by utilizing WLP techniques, which is tough to break even when handled, is proposed in this research. More than 250‐µm‐deep grooves were fabricated around the lid by deep reactive ion etching. After the lid substrate was bonded on the sensor substrate with a resin, the sensor and lid substrates were respectively polished to 50 and 200 µm thickness. The lids were released along the grooves, and the 50‐µm‐thick strain sensors were able to be fabricated by utilizing WLP techniques. This sensor was used as a diaphragm to measure pressure. The sensors were assembled on a stainless steel housing without breakage. The performance of the developed sensor was almost showed with a conventional pressure sensor. [ABSTRACT FROM AUTHOR]

In the DC-6 GHz band, low-insertion-loss packaging materials were investigated to effectively reduce the heat generated during the working process of the attenuation chip. Based on the working principle of the attenuation chip, when the signal passes through the attenuation chip resistor network, it results in energy loss. This means that the insertion loss of the chip generates heat, which leads to an uneven heat dissipation of the chip and thus functional failure. The microwave characteristics of the packaged joints were investigated using different packaging techniques. The results show that the S21 and S11 of the attenuation chip after nano-silver and Au80Sn20 packaging are optimal in the frequency band of DC-6 GHz, and the insertion loss is low compared with the commonly used packaging materials Sn60Pb40 and Sn96.5Ag3.5, which reduces the heat loss and improves the reliability of the attenuation chip packaging. [ABSTRACT FROM AUTHOR]

In soft electronics, anisotropic conductive adhesive films (ACFs) are the trending interconnecting approach due to their substantial softness and superior bondability to flexible substrates. However, low bonding pressure (≤1 MPa) and fine-pitch interconnections of ACFs become challenging while being extended in advanced device developments such as wafer-level packaging and three-dimensional multi-layer integrated circuit board assembly. To overcome these difficulties, we studied two types of ACFs with distinct conductive filler sizes (ACF-1: ~20 μm and ACF-2: ~5 μm). We demonstrated a low-pressure thermo-compression bonding technique and investigated the size effect of conductive particles on ACF's mechanical properties in a customized testing device, which consists of flexible printing circuits and Flex on Flex assemblies. A consistency of low interconnection resistance (<1 Ω) after mechanical stress (cycling bending test up to 600 cycles) verifies the assembly's outstanding electrical reliability and mechanical stability and thus validates the great effectiveness of the ACF bonding technique. Additionally, in numerical studies using the finite element method, we developed a generic model to disclose the size effect of Au/Ni-coated polymer fillers in ACF on device reliability under mechanical stress. For the first time, we confirmed that ACFs with smaller filler particles are more prone to coating fracture, leading to deteriorated electrical interconnections, and are more likely to peel off from substrate electrode pads resulting in electrical faults. This study provides guides for ACF design and manufacturing and would facilitate the advancement of soft wearable electronic devices. [ABSTRACT FROM AUTHOR]

Purpose: This paper aims to realize the vertical interconnection in 3D radio frequency (RF) circuit by coaxial transitions with broad working bandwidth and small signal loss. Design/methodology/approach: An advanced packaging method, 12-inch wafer-level through-mold-via (TMV) additive manufacturing, is used to fabricate a 3D resin-based coaxial transition with a continuous ground wall (named resin-coaxial transition). Designation and simulation are implemented to ensure the application universality and fabrication feasibility. The outer radius R of coaxial transition is optimized by designing and fabricating three samples. Findings: The fabricated coaxial transition possesses an inner radius of 40 µm and a length of 200 µm. The optimized sample with an outer radius R of 155 µm exhibits S11 < –10 dB and S21 > –1.3 dB at 10–110 GHz and the smallest insertion loss (S21 = 0.83 dB at 77 GHz) among the samples. Moreover, the S21 of the samples increases at 58.4–90.1 GHz, indicating a broad and suitable working bandwidth. Originality/value: The wafer-level TMV additive manufacturing method is applied to fabricate coaxial transitions for the first time. The fabricated resin-coaxial transitions show good performance up to the W-band. It may provide new strategies for novel designing and fabricating methods of RF transitions. [ABSTRACT FROM AUTHOR]

With the advancement of Moore's Law reaching its limits, advanced packaging technologies represented by Flip Chip (FC), Wafer-Level Packaging (WLP), System in Package (SiP), and 3D packaging have received significant attention. While advanced packaging has made breakthroughs in achieving high performance, miniaturization, and low cost, the smaller thermal space and higher power density have created complex physical fields such as electricity, heat, and stress. The packaging interconnects responsible for electrical transmission are prone to serious reliability issues, leading to the device's failure. Therefore, conducting multi-field coupling research on the reliability of advanced packaging interconnects is necessary. The development of packaging and the characteristics of advanced packaging are reviewed. The reliability issues of advanced packaging under thermal, electrical, and electromagnetic fields are discussed, as well as the methods and current research of multi-field coupling in advanced packaging. Finally, the prospect of the multi-field coupling reliability of advanced packaging is summarized to provide references for the reliability research of advanced packaging. [ABSTRACT FROM AUTHOR]

In this paper, a novel through mold via (TMV)-embedded fan-out wafer-level package (FOWLP) technology was demonstrated to manufacture the well-designed Antenna in Package (AiP) with ultrathin thickness (0.04 λ0). Double-sided redistribution layers (RDLs) were employed to build the patch antenna, while a TMV interposer was used to connect the front and back RDLs. By optimizing the AiP's parameters, the patch antenna can achieve a wide impedance bandwidth of 17.8% from 24.2 to 28.5 GHz, which can cover the 5G frequency bands. Compared with previous works, the proposed AiP has significant benefits in terms of its ultralow profile, easy processing, and high gain. Hence, the TMV-embedded FOWLP should be a promising technology for fifth generation (5G) millimeter wave (mm-Wave) applications. [ABSTRACT FROM AUTHOR]

The exponential growth of global data traffic is driven by the unprecedented digitalization of the world. To meet the demands of next‐generation high‐capacity data communication systems, innovative solutions are required. Silicon photonics has gained significant attention due to its ability to integrate multiple core functions of optical interconnects into small‐scale chips, offering cost‐effective and scalable manufacturing capabilities. By leveraging silicon photonics, it becomes possible to address the challenge of scaling system complexity while reducing size, cost, and energy consumption. Despite its advantages, silicon has inherent limitations that restrict its application range, such as the weak plasma dispersion effect and relatively large bandgap. Recently, graphene has emerged as a promising solution for traditional silicon photonics because of its exceptional electrical and optical properties. For instance, graphene on a silicon chip enables nearly pure phase modulation and ultrafast photodetection beyond 500 GHz. Moreover, the demonstrated compatibility of graphene with wafer‐level integration paves the way for mass production of graphene‐based silicon photonic devices, offering improved yield, scalability, and cost‐effectiveness. In this work, a comprehensive review is provided, focusing on graphene‐based silicon photonic devices and their applications in optical interconnects, aiming to explore the potential of graphene in advancing silicon photonic technology. [ABSTRACT FROM AUTHOR]

The slide-film damping effect caused by cavity structures is easily neglected in the design of bulk-micro-machined resonant MEMS device fabrication and packaging processes. On the basis of theory calculations, simulations, and actual tests, in this study, we investigate the cavity-depth effect on 3D wafer-level packaged MEMS resonators with the in-plane-motion mode, in which slide-film damping is dominant. On the one hand, it is found that the slide-film damping coefficient is inversely proportional to the cavity depth and remains stable for the cavity depth above a specific value. The critical cavity depth acquired from theoretical results is ~10 µm, which is distinct from that of ~30 µm from simulation results. On the other hand, the variation tendency of simulation results is more in agreement with those of test results for fabricated devices than the theoretical prediction. Hence, before the structure fabrication for a resonator dominated by slide-film damping, it is imperative to choose a conservative cavity depth with a relatively high value from the combination of theory and simulation analyses, so as to ensure the high or desired Q-factors of fabricated resonators, particularly in wafer-level packaging with the low-vacuum or atmospheric pressure. Overall, this work provides not only an analysis strategy on device cavities' slide-film damping but also the optimization design of wafer-level packaging structures and processes. [ABSTRACT FROM AUTHOR]

Inflatable membrane structures are the state-of-the-art fast evolving space structures owing to its inherent advantages such as lightweight, higher packaging efficiency along with ease of deployment. The membrane reflectors need to be actuated by adequate tension forces to get the required surface accuracy. The design of tensioning device has certain challenges, such as mass penalty, low packaging efficiency and power source dependency. The present study demonstrates the novel design methodology for the tensioning system for the inflatable paraboloid membrane reflector antenna using the wave springs. The loading analysis of the inflatable paraboloid reflector is carried out for adequate inflation pressure and tension forces maintaining the surface error within the tolerance limit. The numerical results of the loading analysis are compared and found to be consistent with the experimental findings. The relation between the displacement of tensioning spring and the dimensions of supporting inflatable torus is established. The results show that wave springs can successfully transfer the required tension forces to the reflector with required surface accuracy. The findings of this research provide insights for simple, lightweight, packaging efficient and cost-effective design solution to the tensioning system for inflatable paraboloid reflector antenna. [ABSTRACT FROM AUTHOR]

In this paper, simulation of the structure at some stages of fabrication of a microassembly with embedded dies using FOWLP technology was carried out. The data on the values of thermomechanical deformations and stresses in the structure of the sample consisting of a steel ring, temporary carrier, dies and layers of polyimide and epoxy compound taking into account temperature effects in the manufacturing process route were obtained. The presented results can be used for further improvement of the technological process of chip packaging at the wafer level. [ABSTRACT FROM AUTHOR]

The demand for advanced packaging is driven by the need for low-profile, densely-integrated, large-die Si devices in substrate-based or wafer-level packaging. Die strength is a critical parameter for ultrathin dies, making die singulation a vital aspect of advanced packaging technology. In this work, we present a dicing before grinding (DBG) process to compare and analyze die strengths using a mechanical blade, stealth laser, and plasma dicing. The three DBG processes were applied to a 200 mm silicon (Si) wafer process with a die size of 10 × 10 mm2 and thicknesses of 100, 200, and 300 μm, respectively. Optical and electron microscopes were employed to investigate chipping quality, sidewall damage, and surface contamination. The bare Si die's strength was assessed using a three-point bending test. Plasma dicing before grinding (PDBG) resulted in less contamination, chipping, and cracking compared to other DBG processes. Furthermore, PDBG exhibited the highest die strength of 1052 Pa. [ABSTRACT FROM AUTHOR]

MEMS gyroscopes are widely applied in consumer electronics, aerospace, missile guidance, and other fields. Reliable packaging is the foundation for ensuring the survivability and performance of the sensor in harsh environments, but gas leakage models of wafer-level MEMS gyroscopes are rarely reported. This paper proposes a gas leakage model for evaluating the packaging reliability of wafer-level MEMS gyroscopes. Based on thermodynamics and hydromechanics, the relationships between the quality factor, gas molecule number, and a quality factor degradation model are derived. The mechanism of the effect of gas leakage on the quality factor is explored at wafer-level packaging. The experimental results show that the reciprocal of the quality factor is exponentially related to gas leakage time, which is in accordance with the theoretical analysis. The coefficients of determination (R2) are all greater than 0.95 by fitting the curves in Matlab R2022b. The stable values of the quality factor for drive mode and sense mode are predicted to be 6609.4 and 1205.1, respectively, and the average degradation characteristic time is 435.84 h. The gas leakage time is at least eight times the average characteristic time, namely 3486.72 h, before a stable condition is achieved in the packaging chamber of the MEMS gyroscopes. [ABSTRACT FROM AUTHOR]

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To meet the demands for miniaturization and multi-functional and high-performance electronics applications, the semiconductor industry has shifted its packaging approach to multi-chip vertical stacking. Among the advanced packaging technologies for high-density interconnects, the most persistent factor affecting their reliability is the electromigration (EM) problem on the micro-bump. The operating temperature and the operating current density are the main factors affecting the EM phenomenon. Therefore, when a micro-bump structure is in the electrothermal environment, the EM failure mechanism of the high-density integrated packaging structure must be studied. To investigate the relationship between loading conditions and EM failure time in micro-bump structures, this study established an equivalent model of the vertical stacking structure of fan-out wafer-level packages. Then, the electrothermal interaction theory was used to carry out numerical simulations in an electrothermal environment. Finally, the MTTF equation was invoked, with Sn63Pb37 as the bump material, and the relationship between the operating environment and EM lifetime was investigated. The results showed that the current aggregation was the location where the bump structure was most susceptible to EM failure. The accelerating effect of the temperature on the EM failure time was more obvious at a current density of 3.5 A/cm2, which was 27.51% shorter than 4.5 A/cm2 at the same temperature difference. When the current density exceeded 4.5 A/cm2, the change in the failure time was not obvious, and the maximum critical value of the micro-bump failure was 4 A/cm2~4.5 A/cm2. [ABSTRACT FROM AUTHOR]

This study investigated the impact of material properties of epoxy molding compounds on wafer warpage in fan-out wafer-level packaging. As there is currently a lack of comprehensive discussion on the various material property parameters of EMC materials, it is essential to identify the critical influencing factors and quantify the effects of each parameter on wafer warpage. The material properties include Young's modulus of the epoxy molding compound before and after the glass transition temperature (Tg) range of 25–35 °C (EL) and 235–260 °C (EH), coefficient of thermal expansion (α1, α2), and the temperature change (∆T) between EL and EH. Results show that, within the range of extreme values of material properties, EL and α1 are the critical factors that affect wafer warpage during the decarrier process in fan-out packaging. α1 has a more significant impact on wafer warpage compared with EL. EH, α2, Tg, and ∆T have little influence on wafer warpage. Additionally, the study identified the optimized material property of the epoxy molding compound that can reduce the maximum wafer warpage in the X and Y directions from initial values of 7.34 mm and 7.189 mm to 0.545 mm and 0.45 mm, respectively, resulting in a reduction of wafer warpage of 92.58% (X direction) and 93.74% (Y direction). Thus, this study proposes an approach for evaluating the impact of material properties of epoxy molding compounds on wafer warpage in fan-out wafer-level packaging. The approach aims to address the issue of excessive wafer warpage due to material variation and to provide criteria for selecting appropriate epoxy molding compounds to enhance process yield in packaging production lines. [ABSTRACT FROM AUTHOR]

As the surface acoustic wave (SAW) filters incline to ultrafine, the failures resulting from the wafer molding process have become increasingly prominent. A methodology for coupling the mechanisms of die fly and die shift for the SAW filter miniatured with 737 μ m × 517 μ m × 200 μ m is developed for the trade-off between reliability and yields. In terms of die fly and die shift, the former occurs before the epoxy molding compound (EMC) is cured in the temperature rise period, while the latter occurs in the cooling stage after being cured. The die fly is induced by the fluid flow force in the high-temperature stage of heat compression, which is fatal for the scrap. Followed by the cooling stage, the CTE (coefficient of thermal expansion) misalignment between the die and epoxy molding compound (EMC) seriously affects the die shift and the following lithography process yields. The debonding critical energy in the mixed mode is employed to avert the die fly. Then, the die fly can be shunned by fine-tuning the die thickness, die layout, and EMC layout. A methodology to measure die shift was conducted, by which a total of 47,568 dies were embedded using compression molding. The mechanical error of the mounter and the die shift law are comprehensively leveraged, indicating that the die shift can be controlled within 50 μ m for 8-inch wafer-level packaging. [ABSTRACT FROM AUTHOR]

Due to the advantages of non‐contact processing, high efficiency, high precision, and superior controllability, laser lift‐off (LLO) technologies exhibit excellent material applicability and process compatibility in the lift‐off of ultra‐thin electronic devices. This brings new opportunities for large‐scale manufacturing of emerging electronics that meet ultra‐thin, fragile, and poor high‐temperature resistance. However, this opportunity also comes with formidable challenges from the complex mechanisms of laser‐matter interactions, which hinder comprehensive exploration and fundamental understanding. By elaborating the laser‐material interactions, the photothermal effect, "cold" processing, shockwave effect, and cavitation effect in LLO process from multiple perspectives, this review is devoted to discussing the latest progress and sustainable application of LLO technologies in emerging electronics that are developing toward ultra‐thin, miniaturization, and integration, such as wafer level packaging, displays, energy harvesters, sensors, and memories. Finally, starting from the fundamental principles of material design, light field regulation, and intelligent control system, the challenges and new approaches faced by LLO technologies are explored and fully integrated with future innovative manufacturing concepts and device structures. [ABSTRACT FROM AUTHOR]

This paper outlines the detailed study on the imperfections, which are commonly associated with the realization of Radiofrequency Micro-Electro-Mechanical System (RF-MEMS) devices. It also includes empirical modeling of each phenomenon. These imperfections have been broadly categorized into two major classes: fabrication related and another is linked with IC assembly/packaging method. The thorough study deciphers the insight device physics embedded with all those fabrication and packaging issues in MEMS devices. Individual modeling of these issues gives a clear picture of their impacts on device performances. [ABSTRACT FROM AUTHOR]

In this study, room-temperature wafer bonding of Al2O3 thin films on Si thermal oxide wafers, which were deposited using atomic layer deposition (ALD), was realized using the surface-activated bonding (SAB) method. Transmission electron microscopy (TEM) observations indicated that these room-temperature-bonded Al2O3 thin films appeared to work well as nanoadhesives that formed strong bond between thermally oxidized Si films. The perfect dicing of the bonded wafer into dimensions of 0.5 mm × 0.5 mm was successful, and the surface energy, which is indicative of the bond strength, was estimated to be approximately 1.5 J/m2. These results indicate that strong bonds can be formed, which may be sufficient for device applications. In addition, the applicability of different Al2O3 microstructures in the SAB method was investigated, and the effectiveness of applying ALD Al2O3 was experimentally verified. This successful SAB of Al2O3 thin films, which is a promising insulator material, opens the possibility of future room-temperature heterogenous integration and wafer-level packaging. [ABSTRACT FROM AUTHOR]

In response to the increasing manufacturing complexity/cost in maintaining DRAM advancements through traditional scaling, three-dimensional integrated circuits (3D ICs) and 2.5-dimensional ICs with Si interposers are known as promising candidates to overcome these challenges due to their advantages of low power, small form factor, high density, and high bandwidth. In this work, we present a true process-heterogeneous stacked embedded DRAM (SeDRAM) using hybrid bonding 3D integration process, achieving high bandwidth of 34 GBps/Gbit and high energy efficiency of 0.88 pJ/bit. Moreover, the critical factors of the SeDRAM design are presented (e.g., the low data movement energy, high-density physical interface, simplified protocol definition, process compatibility, density extensibility, and hybrid bonding connection fast test by DFT (design for test). Our results and design methodology have paved the way to realize applications of hybrid bonding to high bandwidth and energy efficiency DRAM. More importantly, the SeDRAM solution can also support the maximum storage density of 48 Gbit and the bandwidth capability of TBps. It can greatly alleviate the "memory wall" problem and thus improve its competitiveness in near-memory computing/computing-in-memory fields. [ABSTRACT FROM AUTHOR]

With the advent of the era of big data and the vigorous development of consumer electronics, the demand for higher-speed processing capacity for gigantic amounts of data is increasing; this requires finer and far more numerous connections between dies as an essential component for connection and electronic communication between layers. The coplanarity of the height of micro bumps is crucial to ensure the reliability of the chip. The triangulation method has been widely used in various types of visual inspection applications over the past several years due to its high measurement accuracy and fast detection speed. In this paper, the application of triangulation technology is analyzed and used in micro bump height measurement. The measurement system proposed consists of a delicate design, a linearly arranged light projection module and a high-quality imaging module. Along the light stripe, multiple-height data of micro bumps are collected in a frame, and the full-field measurement is realized as the wafer is driven by the high-precision motional stage, following the optimal measurement route planned previously. In the scanning process, the images of the light strip projected on the top and bottom of the micro bumps are simultaneously acquired by the sophisticated micro vision system, and then the heights of micro bumps are calculated from a simple formula based on the geometry of the specimen and the system configuration. The experimental results demonstrate that the measuring deviation of the micro bump height has an accuracy of 1.5 μm. [ABSTRACT FROM AUTHOR]

Most microsensors are composed of devices and covers. Due to the complicated structure of the cover and various other requirements, it difficult to use wafer-level packaging with such microsensors. In particular, for monolithic microsensors combined with read-out ICs, the available process margins are further reduced due to the thermal and mechanical effects applied to IC wafers during the packaging process. This research proposes a low-temperature, wafer-level vacuum packaging technology based on Cu-Sn bonding and nano-multilayer getter materials for use with microbolometers. In Cu-Sn bonding, the Cu/Cu3Sn/Cu microstructure required to ensure reliability can be obtained by optimizing the bonding temperature, pressure, and time. The Zr-Ti-Ru based nanomultilayer getter coating inside the cap wafer with high step height has been improved by self-aligned shadow masking. The device pad, composed of bonded wafer, was opened by wafer grinding, and the thermoelectrical properties were evaluated at the wafer-level. The bonding strength and vacuum level were characterized by a shear test and thermoelectrical test using microbolometer test pixels. The vacuum level of the packaged samples showed very narrow distribution near 50 mTorr. This wafer-level packaging platform could be very useful for sensor development whereby high reliability and excellent mechanical/optical performance are both required. Due to its reliability and the low material cost and bonding temperature, this wafer-based packaging approach is suitable for commercial applications. [ABSTRACT FROM AUTHOR]

Emerging trends like the Internet of Things require an increasing number of different sensors, actuators and electronic devices. To enable new applications, such as wearables and electronic skins, flexible sensor technologies are required. However, established technologies for the fabrication of sensors and actuators, as well as the related packaging, are based on rigid substrates, i.e., silicon wafer substrates and printed circuit boards (PCB). Moreover, most of the flexible substrates investigated until now are not compatible with the aforementioned fabrication technologies on wafers due to their lack of chemical inertness and handling issues. In this presented paper, we demonstrate a conceptually new approach to transfer structures, dies, and electronic components to a flexible substrate by lift-off. The structures to be transferred, including the related electrical contacts and packaging, are fabricated on a rigid carrier substrate, coated with the flexible substrate and finally lifted off from the carrier. The benefits of this approach are the combined advantages of using established semiconductor and microsystem fabrication technologies as well as packaging technologies, such as high precision and miniaturization, as well as a variety of available materials and processes together with those of flexible substrates, such as a geometry adaptivity, lightweight structures and low costs. [ABSTRACT FROM AUTHOR]

Copper (Cu) is the metal of choice for the redistribution layer (RDL) to facilitate fast I/O communication in an integrated circuit (IC). Cu can electrochemically migrate (ECM) between the array of electrodes under bias, electrolyte, and moisture. IC packages fail miserably when exposed to various ion impurities and moisture. Copper at the anode dissolves to form Cu+1 and Cu+2 ions. As the anodic dissolution continues, the concentration of copper ion increases. These anions deposit on the cathode leading to Cu dendrite formation. To achieve the nearzero parts per billion defectivity goal, elimination of ECM defects in packaged devices is critical. This work discusses the development of a novel Cu-selective passivation and a method to accelerate reliability testing. A hydrophobic passivation with minimum stress to the IC package is proposed in this work. The new passivation coating is thermally stable, strongly adheres to Cu, is corrosion resistant, low cost, and shows good potential to prevent ECM defects. The coated packaged devices were tested by an accelerated PEG drop test (PDT) to explore its ECM prevention capabilities. [ABSTRACT FROM AUTHOR]

Atomic devices such as atomic clocks and optically-pumped magnetometers rely on the interrogation of atoms contained in a cell whose inner content has to meet high standards of purity and accuracy. Glass-blowing techniques and craftsmanship have evolved over many decades to achieve such standards in macroscopic vapor cells. With the emergence of chip-scale atomic devices, the need for miniaturization and mass fabrication has led to the adoption of microfabrication techniques to make millimeter-scale vapor cells. However, many shortcomings remain and no process has been able to match the quality and versatility of glass-blown cells. Here, we introduce a novel approach to structure, fill and seal microfabricated vapor cells inspired from the century-old approach of glass-blowing, through opening and closing single-use zero-leak microfabricated valves. These valves are actuated exclusively by laser, and operate in the same way as the "make-seals" and "break-seals" found in the filling apparatus of traditional cells. Such structures are employed to fill cesium vapor cells at the wafer-level. The make-seal structure consists of a glass membrane that can be locally heated and deflected to seal a microchannel. The break-seal is obtained by breaching a silicon wall between cavities. This new approach allows adapting processes previously restricted to glass-blown cells. It can also be extended to vacuum microelectronics and vacuum-packaging of micro-electro-mechanical systems (MEMS) devices. [ABSTRACT FROM AUTHOR]

The integrated fan-out (InFO) wafer-level chip-scale package (WLCSP) is introduced for modern system-in-package designs with larger I/O counts, higher interconnection density, and small form factors. A redistribution layer (RDL) in an InFO package is an extra metal layer for interchip connections, and RDL routing is crucial for achieving desired interchip connections. In a high-density InFO package, multiple RDLs with flexible vias are often adopted. To integrate chips of different technology nodes into one package, irregular pad structures need to be considered; however, no published RDL routing work considers flexible vias or irregular pad structures. This article formulates a new RDL routing problem with unified-assigned pad pairs on a via-based multilayer multichip InFO package with irregular pad structures and presents the first algorithm for this problem. The algorithm consists of a preprocessing stage, three routing stages, and a layout optimization stage. The preprocessing stage analyzes routing resources and potential routing congestion. The first routing stage performs layer assignment based on a weighted maximum planar subset of chords algorithm to route interchip nets concurrently. The second routing stage constructs a 3-D routing graph based on partitioned octagonal tiles to handle the irregular layout structure and applies A*-search to route remaining interchip nets. The third routing stage transforms a routing graph into a network-flow model to perform concurrent routing for chip-to-board nets by applying the minimum-cost maximum-flow algorithm. Finally, we develop an efficient linear-programming-based layout optimization algorithm to find desired solutions. Experimental results show that our router can achieve 100% routablility for all benchmarks under limited RDLs, while the previous state-of-the-art work cannot. [ABSTRACT FROM AUTHOR]

In this study, we propose an algorithm that complements the frequency dependence of the relative permittivity conversion equation applied for the measurement of relative permittivity through a ring resonator. The broadband electrical characteristics of an epoxy molding compound (EMC) used in the fan-out wafer-level packaging (FOWLP) process were measured using our algorithm. By proposing a formula for calculating the permittivity that reflects the current distribution at the multiplied frequency of the microstrip ring resonator, the effective range of the permittivity of the sample was extended to the multiplied frequency region. Thus, a more sophisticated and effective complex permittivity was calculated over a wide band. The relative permittivity of the EMC measured by the proposed techni- que was 3.836 and the dielectric loss tangent was 0.022. This technique improved the relative permittivity measurement error rate by 3.95 % and the measurement error rate of the dielectric loss tangent by 8.4 %p compared to the conventional method. [ABSTRACT FROM AUTHOR]

The vacuum chamber is an important part of microparticle optical levitation technology. The traditional vacuum chamber has a large volume and many peripheral components, which cannot meet the requirements of miniaturization and on-chip optical levitation technology. Therefore, this study proposes a novel microparticle vacuum chamber based on the micro-electro-mechanical system (MEMS) process. This MEMS microparticle vacuum chamber adopts a "glass-silicon-glass" three-layer vacuum bonding process, with a volume of only 15 mm × 12 mm × 1.2 mm, including particle chamber, cantilever resonator chamber, and getter chamber, which can encapsulate microparticles in a tiny vacuum environment and realize optical levitation of microparticles. At the same time, the air pressure in the micro vacuum chamber is monitored by the cantilever resonator, which can provide a miniaturized microparticle chamber with a more accurate vacuum environment for microparticle optical levitation. The research of this paper has significance for promoting the development of miniaturized optical levitation technology. [ABSTRACT FROM AUTHOR]

This paper presents the design of a novel 3×3 piezoelectric micromirror array (PMMA) with an 84.6 % fill factor and describes a three-dimensional hidden fabrication platform. The fabricated device operates with quasi-static mode in 3-degree-of-freedom, namely tip, tilt, and piston. In order to achieve a high fill factor, a three-dimensional hidden micromirror array structure is introduced, and is realized through multi-layer bonding. In addition, a double-stop-layer's glass cover for optical device was employed to realize transparent wafer-level packaging. The device testing result achieves a mechanical tilting angle of 4.4 mrad at 82.5 V DC with over 99.5 % linearity. This design has the potential to achieve a larger size of micromirror arrays. [Display omitted] • The preparation of 3-dimensional hidden highly fill factor (84.6%) micromirror arrays (3×3) has been realized by multi-wafer bonding. • The micromirror arrays have the same resonant frequency (862.5Hz), excellent linearity (above 99%) and minimum angular resolution (20μrad@30mV for the x-axis and 29μrad@30mV for the y-axis). [ABSTRACT FROM AUTHOR]

• Creep constitutive model incorporating time–temperature-moisture equivalence principles. • Degradation of interfacial fracture toughness caused by moisture absorption time. • Quantitative method for prediction of PI-RDL delamination in FOWLP under uHAST. Fan-Out Wafer-Level Packaging (FOWLP) is increasingly utilized for its superior performance, facilitated by flexible heterogeneous integration. Despite its advantages, the interface between Polyimide (PI) and Redistribution Layers (RDL) is susceptible to significant vulnerabilities, notably delamination. This study introduces a quantitative method to assess PI-RDL interface delamination in FOWLP under unbiased Highly Accelerated Stress Tests (uHAST), a standard approach in accelerated reliability testing characterized by high humidity and temperature. Central to our methodology is the development of a time–temperature-moisture equivalence-based creep constitutive model, which significantly enhances our understanding of the impact of temperature and moisture on creep behavior. Furthermore, we have developed an innovative "open moisture absorption" method for preparing samples for four-point bending tests, enabling precise quantification of the time-induced degradation of PI-RDL interfacial fracture toughness under saturated conditions. Our comprehensive finite element model integrates moisture diffusion, the newly developed creep constitutive model, and solid mechanics to accurately simulate the accumulation of strain energy release rate during uHAST, facilitating precise predictions of delamination initiation times in FOWLP. Experimental validation under two uHAST conditions—130 °C/85 %RH for 96 h and 110 °C/85 %RH for 264 h—demonstrates the effectiveness of our approach, predicting the delamination initiation time at the PI-RDL interface with over 80 % accuracy. This predictive methodology is pivotal in enhancing the structural optimization and extending the service life of FOWLP in varied environmental conditions. [ABSTRACT FROM AUTHOR]

In this paper, a MEMS resonant vacuum gauge (MRVG) based on the squeezed film damping is proposed and its theoretical measurement model is established. The sensitive structure and electrodes of the MRVG were fabricated on SOI wafers and were wafer level packaged including intake hole. An resonance excitation and capacitive detection circuit consists of capacitive voltage converter (C/V) module, PLL and modulation and demodulation module was designed. Experimental tests were carried out in a standard vacuum calibration chamber, and the measurement results verified the theoretical model. The indication accuracy of the MRVG is less than ± 20 % in the vacuum range of 9 × 1 0 − 5 Pa ∼ 1 Pa. Moreover, the output voltage is still not saturated at the highest vacuum level (9 × 1 0 − 5 Pa), which lays the foundation for subsequent measurement of higher vacuum levels. • The vacuum pressure of 9 × 1 0 − 5 Pa was measured by MEMS structure. • A resonant structure is used to characterize the squeezed film damping. • A reverse torsion pendulum type mass block structure is used as the resonator. • The indication accuracy is less than ± 20 % in range of 9 × 1 0 − 5 Pa ∼ 1 Pa. [ABSTRACT FROM AUTHOR]

Die shift in fan-out wafer-level packaging (FOWLP) is a major roadblock, limiting package scaling and performance. It not only limits the wire pitch but also results in reliability problems and yield loss. In this work, we systematically investigate and predict the in-plane and out-of-plane die shift through numerical and experimental analysis in FlexTrate, which is a flexible hybrid electronics (FHE) platform based on FOWLP for flexible heterogeneous integration. First, the in-plane die shift is studied through simulation of the molding process and the substrate cure shrinkage. The molding process is simulated through a fluid analysis which explores the shear force. In addition, a thermo-mechanical analysis simulates the polydimethylsiloxane (PDMS) curing process followed by handler release. Based on this model, the effect of die size, die spacing, die thickness, and PDMS thickness on die shift are analyzed. The results indicate that smaller die size has a larger impact on die shift compared to the other factors. The predicted die shift is compared with the experimental results to verify the validity. Further, the experimental characterization of out-of-plane die shift is analyzed through the study of substrate warpage and die placement force which reveal the deleterious effect of high temperature processes. Finally, using the developed numerical model, the die placement is optimized for a surface electromyography (sEMG) system. This detailed analysis sheds light on the various factors which influence die shift, and hence is an important step to push the boundaries of current FHE to new limits. [ABSTRACT FROM AUTHOR]

A sandwich structure, which is stacked by a wafer-level copper–copper (Cu–Cu) thermocompression bonding and a silicon–silicon (Si–Si) direct bonding, has been investigated for potential application as a hermetic seal in 3-D microsystem packaging. First, the bottom and middle layers are prebonded by hydrophilic Si direct bonding. Oxygen plasma is employed for surface activation. Then, the prebonded wafers and the top wafer are bonded via Cu thermocompression bonding at a bonding temperature of 300 °C and a bonding force of 8000 mbar for a duration of 1 h. The entire bonding process of the three layers has borne only one heating procedure, which could effectively reduce the residual stress after bonding. Cavities are etched to a volume of $21.4\times 10^{-3}$ cm3 following the MIL-STD-883E standard prescribed for microelectronics packaging. The helium leak test demonstrates that 96.8% of the samples present a superior leak rate smaller than $1.7\times 10^{-8}$ atm $\cdot $ cm3/s. Moreover, the interfacial adhesion energy between the Cu–Cu bonding interface and the Si–Si bonding interface was projected at 16.4 ± 4.6 J/ $\text{m}^{2}$ and Si breakage energy. The results hold great promise for 3-D microsystem wafer-level packaging. [ABSTRACT FROM AUTHOR]

We explore compatibility of Ru with Al-Ge eutectic wafer bonding. We first present experiments to check for the presence of Ru ternary alloy poisoning inhibiting Al-Ge melting as well as evaluations of Al-Ge melt wettability on Ru and diffusion outcomes following bond-simulating anneals. Results show that Ru is stable with no observed microstructural changes or dissolution in the melt, indicating no ternary poisoning for the applied thermal budget. Ru was found to act as an effective barrier offering good melt wettability in all considered configurations with Al and Ge. From inspection of the binary constituents of Al-Ge-Ru we propose that Al-Ge eutectic melting temperature will decrease marginally for Ru contamination in a 1-2% range before a drastic increase in melting temperature (>10°C/% Ru) at higher Ru compositions. We then demonstrate wafer-level packaged 200 mm devices and MEMS with strong bond outcomes of devices bearing Ru contacts. We conclude that Ru has high compatibility with Al-Ge eutectic bonding. [2022-0037] [ABSTRACT FROM AUTHOR]

Packaging radio-frequency microelectromechanical systems (RF-MEMS) is mandatory for their integration in electronic systems. This paper discusses the integration of a Au−Ru/AlCu contact in a MEMS fabrication process with a wafer-level packaging (WLP) step through Al−Ge eutectic bonding. The Au contact is embedded in a movable fixed−fixed beam made of $30 ~ \mu \text{m}$ thick Si while Ru is used as a coating metal on top of the AlCu static electrode. The measured return loss and isolation of the contact, up to 40 GHz, are $\geq -1.7$ and $\leq -12$ dB respectively. The WLP Au−Ru/AlCu contact has an electrical resistance $\leq 1.2 ~ \Omega $ up to 3 million cycles in hot switching at 0.1 W before failing due to high electrical resistance. Au hillocking is identified as the only intrinsic limiting mechanism that can be mitigated by an appropriate design rule. It is demonstrated that Au−Ru/AlCu is a promising contact configuration, compatible with Al−Ge eutectic bonding, and can be integrated in a standard MEMS fabrication process flow for the development of a robust generation of WLP RF-MEMS. [ABSTRACT FROM AUTHOR]

In this paper, we present wafer-level packaging technology for surface acoustic wave (SAW) filters with higher long-term reliability and better electrical performance. This article focuses on the package structure, fabrication processes, and reliability for the SAW filter wafer-level package (WLP). The key processes, including cavity wall (CW) dam formation through non-photosensitive film vias development using a laser drilling process, a redistribution layer (RDL), and ball-grid array formation are developed. In addition, a numerical study based on the finite element model has been conducted to analyze the stress distribution of Cu RDL traces. In addition, the CW dam and the roof layer are covered with polymer, which solves the delamination problem between the CW dam and the substrate. Meanwhile, after practical verification, the SAW filter WLP was resistant to encapsulating pressure using a high elastic modulus capping material, which solved the collapse problem. Additionally, a comparison of the RF filter package's electrical performance following the preconditional level 3 and unbiased highly accelerated stress test revealed no differences in insertion attenuation across the passband (<0.2 dB, standard value: 1 dB). The final packages passed the reliability tests in the field of consumer electronics. [ABSTRACT FROM AUTHOR]

Antenna-in-package (AiP) has been widely applied for millimeter wave system integration. Fan-out interconnection provides low parasitic parameters and is the most suitable technology for monolithic microwave integrated circuit (MMIC) packaging. Thermal design should be considered due to high power consumption of mm-wave chips. For compact AiP system, arrangement of heat sink should not influence radiation performance. In this work, an AiP topology is proposed using 3-D fan-out integration, miniature horn antenna is adopted as heat sink with relative high gain and wide band. A small sized organic substrate board is embedded in molding compound for right-angle transition of millimeter wave signal. Choke structure is designed at the bottom surface of metal horn with improved transition performance. Two horn antennas are designed with measured gain 11.5 and 15.4 dB, respectively, bandwidth under return loss −10 dB is higher than 16.7% for 60 GHz wireless communication. The AiP system has been manufactured and measured on test board with well-functioned radiation performance. Thermal dissipation model is analyzed, measured results under 340 mW power consumption are consistent with simulation. [ABSTRACT FROM AUTHOR]

This article confirms the advantage of fan-out (FO) packaging in the electrical performance of power delivery among integrated circuit (IC) chips with the best use of land side capacitors (LSCs). On-chip in-place waveform measurements quantitatively evaluate the integrity of powering and signaling within FO wafer level packaging (FOWLP) multiple chip module (MCM) demonstrators, where a pair of IC chips are assembled with LSCs with different sizes and structures. The IC chip incorporates an array of 12 digital cores and on-chip waveform monitor (OCM) circuits. Each digital core consists of a low-voltage differential signaling (LVDS) transceiver channel that is backed by a static random access memory (SRAM)-based built-in self test (BIST) module and supplied by an on-chip voltage regulator module (VRM). The LSCs are placed on the bottom side of an FO interposer and inserted between the output of VRM and the ground plane almost ideally with the shortest length of physical traces. A Si membrane capacitor of 10 nF sustains the lowest power line impedance over the frequency range of 2.0 GHz more constantly than a multilayer ceramic counterpart, and attenuates the high-order harmonic frequency components to the clocking frequency at 750 MHz. The leverage of LSCs in powering also improves signaling and helps achieve the wider eye openings in LVDS channels. The implications are elaborated for the capacitor selections with respect to the physical types of capacitors, the size of capacitances, and the level of shares in power delivery among digital cores, all toward the higher level of integrity in powering and signaling in FOWLP MCMs. [ABSTRACT FROM AUTHOR]

One of the most significant challenges for the fabrication of any microelectro-mechanical-system (MEMS) device is the low cost and high throughput packaging of the device to protect it from the environmental particles, moisture, and contaminations. In this work, an RF-MEMS switch for millimeter-wave (mm-wave) applications is monolithically integrated into the aluminum-based back-end-of-line (BEOL) of a 130-nm bipolar CMOS (BiCMOS) technology by wafer-level thin-film encapsulation (WLE). Both wet and vapor release techniques are developed and demonstrated for the release of the MEMS device, prior to wafer-level encapsulation packaging. The final device encapsulation is realized as wafer-level packaging with a 3- $\mu \text{m}$ thick metal grid using a stack of Ti/TiN/AlCu/Ti/TiN layers. Finally, a silicon dioxide deposition process with a high deposition rate (HDR) is applied for the full encapsulation of the release holes. The impact of the encapsulation on the RF-MEMS switch performance is evaluated by low-frequency $C$ – $V$ and high-frequency $S$ -parameter measurements at $D$ -Band. The results indicate the full function of the device without a significant performance drop. The encapsulation does not require an extra mask and it is developed as 8-in wafer-level process, thus providing a low cost and high throughput solution for RF-MEMS device encapsulation and packaging. [ABSTRACT FROM AUTHOR]

With the increasing demand for electronic products, the electronic package gradually developed toward miniaturization and high density. The most significant advantage of the Wafer-Level Package (WLP) is that it can effectively reduce the volume and footprint area of the package. An important issue in the design of WLP is how to quickly and accurately predict the reliability life under the accelerated thermal cycling test (ATCT). If the simulation approach is not adopted, it usually takes several ACTCs to design a WLP, and each ACTC will take several months to get the reliability life results, which increases development time considerably. However, simulation results may differ depending on the designer's domain knowledge, ability, and experience. This shortcoming can be overcome with artificial intelligence (AI). In this study, finite element analysis (FEA) is combined with machine learning algorithms, e.g., Kernel Ridge Regression (KRR), to create an AI model for predicting the reliability life of electronic packaging. Kernel Ridge Regression (KRR) combined with the K-means cluster algorithm provides a highly accurate and efficient way to obtain AI models for large-scale data sets. [ABSTRACT FROM AUTHOR]

This paper presents the design, fabrication and packaging of RF MEMS switches that have CPW-converted-to-microstrip RF interface at the die level. With microstrip input and output ports the packaging of the dies become greatly simplified, doing away with the need for having off-chip matching and RF transition components inside the package. Two designs are presented, each based on a different philosophy for conversion of the inherent CPW version of the chip to microstrip planar transmission line; i) conversion to microstrip through RF matching, ii) CPW to microstrip on-chip via less transition. Detailed 3D EM simulation based studies were carried out to arrive at the final RF layouts. The switches were fabricated using the silicon on glass architecture and packaged in hermetic RF packages at 1 atm N 2 . Wafer level and post packaging test methods are described. Over the range DC to 10 GHz, the worst case packaged device insertion loss, return loss and isolation are −1.2 dB, −13 dB, −37.5 dB for the first design variant of the switch and are −1.2 dB, −11 dB and −30 dB respectively for the second design variant. The typical pull in voltage is 50 V. [ABSTRACT FROM AUTHOR]