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Electron paramagnetic resonance (EPR) and capacitance-voltage measurements have been combined to identify the chemical nature and charge state of defects in BESOI (bonded and etchback silicon-on-insulator) and SIMOX (separation by implantation of oxygen) materials. The four types of defect centers observed, charged oxygen vacancies, delocalized hole centers, amorphous-Si centers, and oxygen-related donors, are strikingly similar. In the BESOI materials, the radiation-induced EPR centers are located at or near the bonded interface. Therefore, the bonded interface is a potential hole trap site and may lead to radiation-induced back-channel leakage. In SIMOX materials, it is found that all of the defects in the buried oxide are due to excess Si. The results using poly-Si/thermal oxide/Si structures strongly suggest that it is the postimplantation, high-temperature anneal processing step in SIMOX that leads to their existence. The anneal leads to the out-diffusion of oxygen from the buried oxide, creating excess-Si related defects in the oxide and O-related donors in the underlying Si substrates. A relatively new class of defects in SiO/sub 2/, delocalized spin centers, are found to be hole traps in both SIMOX and BESOI materials. >

Wafer bonding in semiconductor technology is reviewed. Potential applications of this technique, already demonstrated in research labs, range from high performance SOI CMOS circuits and high voltage or power devices to on-chip microsensors and integration of III–V materials with Si substrates. A summary of the bonding kinetics, as well as methods of the device film formation is given. The quality of the film is discussed, along with common problems encountered in this technology.

The response of the buried oxide in bonded and etched-back silicon-on-insulator (SOI) wafers to radiation doses up to 2 Mrad(Si) was measured. The results indicate that the hardness of the buried oxide can be very good, at least that of a good thermally grown oxide, with only small effects from the bond. The amount of charge created in the buried oxide was independent of the thickness of the buried oxide. The buried oxide can easily be made hard enough to prevent back-channel turn-on in nonfully-depleted FETs at doses of at least 2 Mrad(Si). >

Shallow electron and deep hole trapping in the buried oxides of SIMOX (separation by implantation of oxygen), ZMR, and BESOI (bond and etchback silicon-on-insulator) material are examined. By irradiating the oxides with X-rays at cryogenic temperatures, 40-50 K, hole motion is frozen and electrons are trapped. The oxide charge is determined by C-V measurements. Following the cryogenic irradiation, the electrons are detrapped by field stressing (tunneling) or by annealing (thermal excitation). Hole trapping is examined by annealing after the trapped electrons are removed by field stressing. Substantial shallow electron and deep hole trapping distributed uniformly through the oxide is observed for all buried oxides that are processed above about 1100 degrees C. A comparison to thermal oxides grown at 850 degrees C and annealed at 1300 degrees C with and without a polysilicon capping layer shows that the top silicon layer significantly increases trap formation. These results indicate that the oxide defects responsible for the electron and hole trapping are produced by chemically reducing the oxide and producing defects such as Si-Si pairs. >

A novel silicon-on-insulator technique utilizing the bonding of oxidized silicon wafers has been investigated. The bonding was achieved by heating in an inert atmosphere a pair of wafers with hydrophilic surfaces, which had been contacted face-to-face. A quantitative method for the evaluation of the surface energy of the bond based on crack propagation theory was developed. The bond strength was found to increase with the bonding temperature from about 60-85 erg/cm/sup 2/ at room temperature to approximately=2200 erg/cm/sup 2/ at 1400 degrees C, which is in the same range as the cohesive energy of bulk quartz. The strength was essentially independent of the bond time. Bonds created during a 10 s annealing at 800 degrees C were strong enough to withstand both the thinning of the top wafer to the desired thickness and the subsequent device processing. Three distinct phases of the bonding process were observed. The electrical properties of the bond between the wafers were tested using MOS capacitors. The results were consistent with a negative charge density at the bond interface of approximately 10/sup 11/ cm/sup -2/. A double etch-back procedure was used to thin the device wafer to the desired thickness. The characteristics of the resulting film are described. CMOS devices made in a 0.3- mu m-thick layer had subthreshold slopes of 68 mV/decade (for both n- and p-channel MOS transistors). The effective carrier lifetime was >30 mu s in 300-nm-thick Si films, and the interface state density at the Si-film/buried oxide interface was >

Using electron paramagnetic resonance we have been able to identify a new oxygen‐related donor defect in the Si substrate of bonded and etchback silicon‐on‐insulator structures. This axially symmetric donor is preferentially aligned along the [100] direction, and resides close to the Si/SiO2 interface. It is tentatively suggested that the donors result from the nonoxidizing anneal received by the wafers during the bonding process.

We have investigated fundamental material issues that may impact device performance in bonded and etchback SOI (BESOI) wafers using electron paramagnetic resonance (EPR) measurements. We report a new defect identified as an oxygen-related donor in the virgin Si substrates. The donor appears to result from the anneal during the bonding process, not from the actual bonding procedure. >

Summary form only given. In this work we focus on the characterization of the low dose SIMOX from the designed experiment. In this experiment the oriented, p-type silicon wafers were implanted with the range of doses from 0.3E18 cm/sup 2/ to 0.6E18 cm/sup 2/ at the energy 190 keV, 200 keV and 210 keV and annealed for 6 hours at 1350/spl deg/C in 1%O/sub 2/ in N/sub 2/. Nondestructive characterization was performed using spectroscopic ellipsometry, optical reflectometry and TXRF. The structure of thin film layers was analyzed with high resolution SEM, dislocation density was determined by the enhanced Secco etch, and buried oxide integrity was examined by the measurements of I/V and C/V characteristics with the mercury probe analyzer.

This paper deals with the use of reactively sputtered aluminum nitride (AlN) films as insulators for Bond and Etch-back Silicon-On-Insulator (BESOI) materials. In SOI-applications where high power is dissipated in the silicon SOI-film the low thermal conductivity of the buried silicon dioxide layer may cause a temperature rise in the silicon film detrimentally affecting the device performance. An attractive alternative would be to replace the silicon dioxide of the SOI structure with another material, like diamond, silicon carbide or aluminum nitride. The thermal conductivity of AlN is considerably larger than that of Si0/sub 2/. This paper presents results on how sputter deposition of AlN may be combined with wafer bonding for the creation of highly thermally conductive SOI structures.

In wafer bonding work directed toward SOI (silicon-on-insulator) technology, an insulating material, usually SiO/sub 2/, present on one or both silicon wafers is sandwiched between the wafers upon bonding. Subsequent thinning of one of the wafers produces a monocrystalline film of desirable thickness separated from the substrate by the insulator. A method based on the theory of crack propagation has been devised to quantitatively study the bonded interface. In the particular case of oxidized silicon wafers, the bonding exhibits three different phases: a hydrogen-bond process dominates low temperature bonding; Si-O-Si bond formation accompanied by elastic wafer deformation occurs at the intermediate temperatures; and Si-O-Si bond formation is supported by plastic flow of the oxide at the highest temperatures. For most of the wafer bonding applications a controlled thinning of one of the wafers in the pair is required for the formation of a device film. >

An extensive effort has been undertaken to benchmark the quality of the 200 mm SOI substrates, involving all viable sources of the material in the world. A comprehensive overview of the state of the art of all pertinent parameters of this material is given. The quality of the recent material appears very competitive with the bulk material. In particular, the level of defects in the SOI film is comparable to bulk, below 0.1/cm/sup 2/ for the best material. SOI wafer processing will require only minor equipment and process adjustments. The main challenges for the SOI material today is a sustainable consistency of its parameters, the price and volume availability.

We have conducted an investigation to evaluate the impact of both touch-polish and hydrogen annealing at different temperatures on the roughness, on the SOI film removal, as well as the impact of so processed surface on the integrity of gate oxide thermally grown on it, for SIMOX and BESOI material.

As thin film SOI (TFSOI) moves from RD however, this data can be process specific and tends to be of limited access. This work applies an enhanced version of Poisson's equation (commonly used to calculate yield vs. defect densities) to examine required defect levels for application of TFSOI to advanced devices. Discrete defects are analyzed including surface particles (light scattering centers, LSC), HF defects, silicon threading dislocations, and buried oxide (BOX) defects. Some measured material data is included to note the present status and highlight potential challenges in achieving required levels.

A 28 volt solenoid driver has been realized in partially-depleted SOI CMOS technology. The design features an n-channel high voltage MOSFET with an extended drain and a polysilicon field plate, and an on-board flyback diode, each capable of sinking 0.5 A of current and dissipating about 1 W of DC power. Pulse-width modulation (PWM) control maintains low dynamic power dissipation in the drive FET, while the externally selectable "pull-in and hold" function, which reduces the maximum operating current, helps to minimize the overall chip power. Saturation detection, current sense, and overcurrent fault outputs are provided to assist the system designer. The device was fabricated on SIMOX wafers with 340 nm of Si film using our 1.25 /spl mu/m CMOS SOI process with single level Ti/W interconnects and CoSi/sub 2/ contacts. Our Ti/W metallization, capped with Si/sub 3/N/sub 4/ for corrosion protection, has been evaluated to have a lifetime of /spl sim/16.7 years for 300/spl deg/C operation at 10/sup 6/ A/cm/sup 2/ (a 10% resistance increase was the definition of failure). The output power transistor has been formed with our standard CMOS process. Its gate dimensions were L=2 /spl mu/m and W=48,000 /spl mu/m, with a drain extension of 2.8 /spl mu/m.

High performance sub-60 nm SOI CMOS transistors have been developed. An aggressively scaled, 1.2 nm thick, gate dielectric sandwich containing silicon nitride and dioxide layers allowed full control of boron penetration with manageable levels of gate leakage. Excellent values of I/sub dsat/ of 850 /spl mu/A//spl mu/m and 500 /spl mu/A//spl mu/m for NMOS and PMOS were respectively obtained at V/sub dd/=1.2 V and I/sub off/=100 nA//spl mu/m. The CV/I metric was 1.0 and 1.9 ps for NMOS and PMOS respectively.

Device modeling data and some early experiments suggests that fully depleted MOSFET devices where channel is controlled by two opposing gates or one gate that surrounds most or the entire channel, will provide better scaling than the classic devices with one gate on one side of the channel. However, formation of such devices requires complex, non-conventional and sometimes exotic geometry and processing, ranging from wafer bonding to selective lateral ‘tunnel’ epitaxy, to selectively wet-etched channels with triangular cross-section. Classic single-gate transistors have been recently demonstrated with reasonable performance at 20-15 nm of physical gate length. Double-gate transistors with their process integration complexity will likely become a viable alternative for smaller geometries. This paper will discuss various approaches to realization of those multi-gate fully depleted devices and their process integration challenges for sub-15 nm gates.

The spectral transmittance, reflectance and emittance of silicon related materials and structures are measured simultaneously utilizing a spectral emissometer operating at near- and mid-IR spectral range and temperature range of 300 to 1500K. Several kinds of samples have been considered here: a) SiO2/Si with oxide in the thickness range of 653–5124A, b) SiO2/Si/ SiO2 with oxide thickness of 5000A on both front and back sides c)Multi-layers of SiO2/Si/ SiO2/poly-Si, with backside oxide of 1600A and 250A, respectively and d) separation by implantation of oxygen (SIMOX), with embedded oxide thickness of 4000A. An extensive analysis has been performed to interpret and compare the results obtained from these measurements.Concerning the SiO2/Si, we find that the experimental results are in accord with the sinusoidal relation of emissivity as a function of the silicon oxide thickness and hence the Applied Materials model. Experimental results on SiO2/Si/SiO2 are also presented here. For the multi-layers of SiO2/Si/SiO2/poly-Si, it is interesting to note that for temperatures above 600°C, the emissivity is independent of temperature and wavelength for the backside oxide thickness of 1600 and 250A. SIMOX measurements are presented as well. The Fiory model has been utilized extensively to investigate the high temperature emissivity data. The applications and limitations of this model are discussed.

Several aspects of a new silicon‐on‐insulator technique utilizing bonding of oxidized silicon wafers were investigated. The bonding was achieved by heating in an inert atmosphere a pair of wafers with hydrophilic surfaces contacted face‐to‐face. A quantitative method for the evaluation of the surface energy of the bond based on crack propagation theory was developed. The bond strength was found to increase with the bonding temperature from about 60–85 erg/cm2 at room temperature to ≂2200 erg/cm2 at 1400 °C. The strength was essentially independent of the bond time. Bonds created during 10‐s annealing at 800 °C were mechanically strong enough to withstand the mechanical and/or chemical thinning of the top wafer to the desired thickness and subsequent device processing. A model was proposed to explain three distinct phases of bonding in the temperature domain. Electrical properties of the bond were tested using metal‐oxide‐semiconductor (MOS) capacitors. The results were consistent with a negative charge de...

Bonding of 3 and 4 in. oxidized silicon wafers was investigated for SOI applications. The bonding was achieved by using a surface treatment procedure compatible with VLSI processing and by heating in an inert atmosphere a pair of wafers which had been contacted face-to-face. A quantitative method for the evaluation of the surface energy of the bond based on crack propagation was developed. The bond strength was found to increase with the bonding temperature from about 60-85 erg/cm2 at room temperature to ⋍2200 erg/cm2 at 1405°C, in good agreement with the surface energy of bulk quartz. The strength was essentially independent of the bond time for up to 1100°C. Electrical properties of the wet-oxide-to-wet-oxide bond were tested using MOS capacitors. The results were consistent with a negative interface charge density of approximately 1011cm−2 at the bond. A double etch-back procedure was used to thin the device wafer to the desired thickness within *20 nm across a 3in. wafer. The density of threading dislocations in the remaining silicon layer was smaller than 103 cm−3, and the residual dopant concentration less than 5×l015cm−3, both remnants of the etchstop layer. A discussion of the bonding mechanism will be presented.

The first experimental results of the temperature dependent radiative properties of separation by implantation of oxygen (SIMOX) wafers, in the literature, have been reported in this study. These measurements have been performed in the temperature range of 17 to 800/spl deg/C and wavelength range of 0.8 to 20 /spl mu/m using a spectral emissometer. A modeling approach based on Multi-Rad, a matrix method of representing multi-layers, has been adopted to interpret the experimental data. Operating ranges of wavelength for pyrometry have been suggested for a reliable monitoring of temperature for processing SIMOX wafers.

Summary form only given. Internal thermal oxidation (ITOX) has been shown to improve the quality of buried oxide (BOX) in low dose (4E17 cm/sup -2/) SOI SIMOX material. SOI film quality of ITOX SIMOX was determined to be as good as bulk in terms of the integrity of gate oxide grown on it. We have investigated low dose SIMOX material and the impact of its high temperature annealing as well as the subsequent ITOX process on structure and electrical properties of its SOI film. Several new findings about the SOI film quality and its relationship to process parameters are reported.