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To increase density of superconductor digital and neuromorphic circuits by 10x and reach integration scale of $10^8$ Josephson junctions (JJs) per chip, we developed a new fabrication process on 200-mm wafers, using self-shunted Nb/Al-AlOx/Nb JJs and kinetic inductors. The process has a layer of JJs, a layer of resistors, and 10 fully planarized superconducting layers: 8 Nb layers and 2 layers of high kinetic inductance materials, Mo$_2$N and NbN, with sheet inductance of 8 pH/sq and 3 pH/sq, respectively. NbN films were deposited by two methods: with $T_c$=15.5 K by reactive sputtering of a Nb target in Ar+N$_2$ mixture; with $T_c$ in the range from 9 K to 13 K by plasma-enhanced chemical vapor deposition (PECVD) using Tris(diethylamido)(tert-butylimido)niobium(V) metalorganic precursor. PECVD of NbN was investigated to obtain conformal deposition and filling narrow trenches and vias with high depth-to-width ratios, which was not possible to achieve using sputtering and other physical vapor deposition (PVD) methods at temperatures below $200 ^oC$ required to prevent degradation of Nb/Al-AlOx/Nb junctions. Nb layers with 200 nm thickness are used in the process layer stack as ground planes to maintain a high level of interlayer shielding and low intralayer mutual coupling, for passive transmission lines with wave impedances matching impedances of JJs, typically, Comment: 12 pages, 16 figures, 4 tables, 49 references. Submitted to IEEE TAS on Nov. 10, 2022

We present measurements of the self- and mutual inductance of NbN and bilayer NbN/Nb inductors with Nb ground plane(s) fabricated in an advanced process for superconductor electronics developed at MIT Lincoln Laboratory. In this process, the signal traces of logic cell inductors are made either of a 200-nm NbN layer with $T_c$=15 K or of an in-situ deposited NbN/Nb bilayer, replacing a 200-nm Nb layer M6 in the standard SFQ5ee process with nine superconducting layers. Nb ground planes were preserved to maintain a high level of interlayer shielding and low intralayer mutual coupling. A two-step patterning of the top Nb and the bottom NbN layers of the NbN/Nb bilayer allows to create inductors in a very wide range of linear inductance values, from low values ~ 0.4 pH/$\mu$m typical for Nb geometrical inductors to ~ 35 pH/$\mu$m typical to thin-film kinetic inductors. Mutual inductance of NbN and Nb inductors, of NbN inductors, and of bilayer inductors is the same as between two Nb inductors with the same geometry and placement between the ground planes, i.e., mutual inductance does not depend on superconducting properties of the signal traces in the studied range of linewidths. We measured magnetic field penetration depth and kinetic inductance of NbN films with thickness t=200 nm to be $\lambda$ = 491+/-5 nm and 1.51 pH/sq, and 2.06 pH/sq at t=150 nm. The kinetic inductance was found to be larger than that expected for superconductors with short mean free path, indicating a reduction in the superfluid density, likely due to carrier localization effects. Kinetic inductance associated with right-angled bends of the NbN inductors is negligible at linewidths $w, Comment: 11 pages, 9 figures, 4 tables, 60 references

Squeezing of the electromagnetic vacuum is an essential metrological technique used to reduce quantum noise in applications spanning gravitational wave detection, biological microscopy, and quantum information science. In superconducting circuits, the resonator-based Josephson-junction parametric amplifiers conventionally used to generate squeezed microwaves are constrained by a narrow bandwidth and low dynamic range. In this work, we develop a dual-pump, broadband Josephson traveling-wave parametric amplifier that combines a phase-sensitive extinction ratio of 56 dB with single-mode squeezing on par with the best resonator-based squeezers. We also demonstrate two-mode squeezing at microwave frequencies with bandwidth in the gigahertz range that is almost two orders of magnitude wider than that of contemporary resonator-based squeezers. Our amplifier is capable of simultaneously creating entangled microwave photon pairs with large frequency separation, with potential applications including high-fidelity qubit readout, quantum illumination and teleportation.

Future astrophysics missions such as the Lynx X-ray Microcalorimeter will comprise a very large array of X-ray microcalorimeters with greater than 100 000 pixels. One of the major challenges associated with the realization of large format arrays is the fabrication of high-density, high-yield, superconducting wiring between the pixels of the array. An attractive way to overcome this challenge is to use buried layers of multilayer wiring. Here we report on the fabrication of prototype arrays of magnetically coupled microcalorimeters (MMCs) using multiple niobium layers of buried wiring. In order to successfully scale MMCs to large arrays, so that the stray inductance of the wiring is sufficiently low and the sensor meander coil inductance is sufficiently high, the meander coil pitch is decreased. We have investigated linewidths as narrow as 400 nm. Fabricated devices have demonstrated high critical currents of 30 mA for the narrowest pitch.

In superconductor electronics fabrication processes developed at MIT Lincoln Laboratory, Josephson junctions (JJs) are placed near the top of the stack composed of nine or ten superconducting layers. We discuss the effects of this placement and other processing factors on uniformity of JJ critical current across 200-mm wafers; specifically, nonuniformity of residual stress in Nb films, wafer bow and warpage caused by accumulated stress in the underlying dielectric and superconducting layers, and effects of accumulated topography caused by patterning and planarization of wiring layers. We describe the typical fabrication defects, focusing primarily on the peculiar defects caused by electrochemical corrosion of dissimilar metals. To increase the integration scale and enhance fabrication capabilities, we are developing a new process, titled SC1, in which Nb/Al/AlO x /Nb JJs are placed near the bottom of the layer stack, preceded only by two planarized layers: resistor layer and superconducting ground plane. Six planarized Nb wiring layers are placed above the JJs. This layer stack should simplify routing of data and clock in integrated circuits, and allow for improvements in uniformity of small JJs. The SC1 process has a 250-nm minimum feature size for inductors, three sheet resistance options for resistors, and two options for JJ critical current density: 100 and 200 μA/μm 2 . We present fabrication details and process optimization aimed at improving JJ uniformity, increasing circuit yield, and reducing occurrence of corrosion defects to below the 1 ppm level.

The ability to localize defects in order to understand failure mechanisms in complex superconducting electronics circuits, while operating at low temperature, does not yet exist. This work applies thermally-induced voltage alteration (TIVA), to a biased superconducting electronics (SCE) circuit at ambient temperature. TIVA is a commonly used, laser-based failure analysis technique developed for silicon-based microelectronics. The non-operational circuit consisted of an arithmetic logic unit (ALU) in a high-frequency test bed designed at HYPRES and fabricated by MIT Lincoln Laboratory using their SFQ5ee process. Localized TIVA signals were correlated with reflected light images at the surface, and these sites were further investigated by scanning electron microscopy imaging of focused ion-beam cross-sections. The areas investigated, where prominent TIVA signals were observed, showed seams in the Nb wiring layers at contacts to Josephson junctions or inductors and/or disrupted junction morphologies. These results suggest that the TIVA technique can be used at ambient temperature to diagnose fabrication defects that may cause low temperature circuit failure.

Data are presented on mutual and self-inductance of various inductors used in multilayered superconductor integrated circuits: microstrips and striplines with widths of signal traces from 250 nm to a few micrometers, located on the same circuit layer at various distances from each other (from 250 nm to a few micrometers) and/or on different layers spaced vertically; effect of long slits in the ground plane(s) along the inductors on their mutual inductance; inductance of right-angled bends; inductance of meanders. Simple analytical expressions for mutual and self-inductance of the basic inductors are given, describing experimental data with accuracy better than 2% in a very wide range of parameters. They can be used for superconductor integrated circuit design and calibration of numerical inductance extractors. Measurements were done using circuits fabricated in fully planarized fabrication processes with eight niobium layers and Nb/Al-AlOx/Nb Josephson junctions, known as the SFQ5ee and SC1 processes developed at MIT Lincoln Laboratory for superconductor electronics. Mutual inductance decreases exponentially with distance between striplines and as a second power of the distance between microstrips, strongly depends on magnetic field penetration depths in superconducting ground planes, whereas superconducting properties of the signal traces are practically immaterial. Weak dependence of mutual inductance on the linewidth of superconducting wires indicates that area of superconducting flux transformers - the essential component of all digital circuits using ac power, superconducting qubits, and sensor arrays - scales poorly with the linewidth, putting a predictable upper limit on the integration scale of such circuits., Comment: 35 pages, 28 figures, 2 tables, 86 references

Data are presented on the inductance of various features used in superconductor digital integrated circuits: microstrip and stripline inductors with linewidths down to 120 nm and different combinations of ground plane layers, effect of perforations of various sizes in the ground planes and their distance to the inductors on inductance, inductance of vias of various sizes between adjacent layers, inductance of composite vias between distant super-conducting layers. Test circuits used for the measurements were fabricated in a new 150-nm node of a fully planarized process with eight niobium layers developed at MIT Lincoln Laborator for superconductor electronics as well as in our standard SFQ5ee and SC1 fabrication processes with 250 nm minimum feature size. The new SC2 process utilizes 193-nm photolithography in combination with plasma etching and chemical mechanical planarization of interlayer dielectrics to define inductors with linewidth down to about 100 nm on critical layers. The standard processes use 248 nm photolithography. The measured data are compared with the results of inductance extraction using soft-ware packages InductEx and wxLC. Variations of circuit inductors caused by the fabrication processes are discussed. Magnetic flux trapping in ground plane moats and its coupling to nearby inductors are discussed for circuit cooling in a residual field of several configurations.

We investigated current–voltage characteristics of unshunted and externally shunted Josephson junctions (JJs) with high critical current densities J c in order to extract their basic parameters and statistical characteristics for JJ modeling in superconducting integrated circuits as well as to assess their potential for future technology nodes. Nb/AlO x -Al/Nb junctions with diameters from 0.5 to 6 μm were fabricated using a fully planarized process with Mo or MoN x thin-film shunt resistors with sheet resistance R sq = 2 Ω/sq and R sq = 6 Ω/sq, respectively. We used our current standard MIT Lincoln Laboratory process node SFQ5ee to fabricate JJs with J c = 0.1 mA/μm2 and our new process node SFQ5hs (where “hs” stands for high speed) to make JJs with J c = 0.2 mA/μm 2 and higher current densities up to about 1 mA/μm2. Using LRC resonance features on the I–V characteristics of shunted JJs, we extract the inductance associated with Mo shunt resistors of 1.4 pH/sq. The main part of this inductance, about 1.1 pH/sq, is the inductance of the 40-nm Mo resistor film, while the geometrical inductance of superconducting Nb wiring contributes the rest. We attribute this large inductance to “kinetic” inductance arising from the complex conductivity of a thin normal-metal film in an electromagnetic field with angular frequency $\boldsymbol{\omega },$ ${{\mathbf \sigma }}(\boldsymbol{\omega }) = {\boldsymbol{\sigma }_0}/({1 + \boldsymbol{i\omega \tau }})$ , where ${{{\mathbf \sigma }}_0}$ is the static conductivity and $\boldsymbol{\tau }$ the electron scattering time. Using a resonance in a large-area unshunted high- J c junction excited by a resistively coupled small-area shunted JJ, we extract the Josephson plasma frequency and specific capacitance of high- J c junctions in 0.1–1 mA/μm2 J c range. We also present data on J c targeting and JJ critical current spreads. We discuss the potential of using 0.2-mA/μm2 JJs in very large scale integration single flux quantum circuits and 0.5-mA/μm2 JJs in high-density integrated circuits without shunt resistors.

A focused ion beam was used to obtain cross-sectional specimens from both magnetic multilayer and Nb/Al-AlOx/Nb Josephson junction devices for characterization by scanning transmission electron microscopy (STEM) and energy dispersive X-ray spectroscopy (EDX). Automated multivariate statistical analysis of the EDX spectral images produced chemically unique component images of individual layers within the multilayer structures. STEM imaging elucidated distinct variations in film morphology, interface quality, and/or etch artifacts that could be correlated to magnetic and/or electrical properties measured on the same devices.

Today, microbump-based flip-chip technology is a compelling option for heterogeneous integration in microelectronic packaging. Performance as well as density (smaller form factor) requirements continue to drive smaller, microbump-based, finer pitch interconnections. This paper presents heterogeneous integration based on microbump fabrication, characterization, and integration for fine pitch die-to-die and die-to-wafer flip-chip interconnection. A variety of microbump options including indium, indium-coated gold, gold and gold-on-gold were used for bump bonding of fine pitch flip-chip structures. A series of microbumps (2.5-15µm) were fabricated using contact and non-contact photolithography on superconducting multi-chip module (S-MCM) wafers. The integration process includes various microbump combinations to reduce microbump spreading / flow during the fine-pitch assembly process. In another study, gold-ball-based interconnects were developed to convert wire bondable chips to a flip-chip process. The use of microbumps to form 10µm-pitch flip-chip interconnects and their initial electrical performance are discussed. As a case study, we have developed indium microbump technology capable of interconnecting an array of 10-to-35-µm-pitch pads to a superconducting multi-chip module (S-MCM) fabricated on 200mm silicon wafers. The S-parameters of several back-to-back microstrip and grounded coplanar waveguide (GCPW) transitions were measured and simulated in a 2.5d (planar) full-wave electromagnetic software package (Sonnet em). The flip-chip configurations showed excellent impedance matching and low insertion loss to multi-gigahertz frequencies. For example, a microstrip-to-microstrip transition using 20µm-diameter bumps with 35µm pitch in a coaxial configuration (signal bump surrounded by ground bumps) had a simulated return loss of less than -20 dB from DC to 23 GHz. By adding some compensating inductance to the transitions, this simulated response was extended to 81 GHz. Smaller bump diameter and pitch yields a much better impedance match and less reflected energy, with the 10 µm pitch and 5 µm bump versions giving near-perfect performance to 100 GHz and beyond. Flip-chipped Josephson junctions and niobium lines interrupted by indium microbumps between the superconducting integrated circuits (ICs) and the S-MCM maintained their I-V characteristics. This paper also discusses large superconducting multi-chip module (S-MCM) fabrication and bonding approaches for future technology. Various fabrication options including jumper flip-chip, stitching and laser direct writing are considered for large S-MCM fabrication.

As research in superconducting electronics matures, it is necessary to have failure analysis techniques to identify parameters that impact yield and failure modes in the fabricated product. However, there has been significant skepticism regarding the ability of laser-based failure analysis techniques to detect defects at room temperature in superconducting electronics designed to operate at cryogenic temperatures. In this paper, we describe preliminary data showing the use of Thermally Induced Voltage Alteration (TIVA) [1] at ambient temperature to locate defects in known defective circuits fabricated using state-of-the-art techniques for superconducting electronics.

We describe recent advances in backside passivation of large-format charge-coupled devices (CCDs) fabricated on 200- mm diameter wafers. These CCDs utilize direct oxide bonding and molecular-beam epitaxial (MBE) growth to enable high quantum efficiency in the ultraviolet (UV) and soft X-ray bands. In particular, the development of low-temperature MBE growth techniques and oxide bonding processes, which can withstand MBE processing, are described. Several highperformance large-format CCD designs were successfully back-illuminated using the presented process and excellent quantum efficiency (QE) and dark current are measured on these devices. Reflection-limited QE is measured from 200 nm to 800 nm, and dark current of less than 1e- /pixel/sec is measured at 40°C for a 9.5 μm pixel.

Recent progress in superconductor electronics fabrication has enabled single-flux-quantum (SFQ) digital circuits with close to one million Josephson junctions (JJs) on 1-cm$^2$ chips. Increasing the integration scale further is challenging because of the large area of SFQ logic cells, mainly determined by the area of resistively shunted Nb/AlO$_x$-Al/Nb JJs and geometrical inductors utilizing multiple layers of Nb. To overcome these challenges, we are developing a fabrication process with self-shunted high-J$_c$ JJs and compact thin-film MoN$_x$ kinetic inductors instead of geometrical inductors. We present fabrication details and properties of MoN$_x$ films with a wide range of T$_c$, including residual stress, electrical resistivity, critical current, and magnetic field penetration depth {\lambda}$_0$. As kinetic inductors, we implemented Mo$_2$N films with T$_c$ about 8 K, {\lambda}$_0$ about 0.51 {\mu}m, and inductance adjustable in the range from 2 to 8 pH/sq. We also present data on fabrication and electrical characterization of Nb-based self-shunted JJs with AlO$_x$ tunnel barriers and J$_c$ = 0.6 mA/{\mu}m$^2$, and with 10-nm thick Si$_{1-x}$Nb$_x$ barriers, with x from 0.03 to 0.15, fabricated on 200-mm wafers by co-sputtering. We demonstrate that the electron transport mechanism in Si$_{1-x}$Nb$_x$ barriers at x < 0.08 is inelastic resonant tunneling via chains of multiple localized states. At larger x, their Josephson characteristics are strongly dependent on x and residual stress in Nb electrodes, and in general are inferior to AlO$_x$ tunnel barriers., Comment: 12 pages, 14 figures, 1 table, 51 references. Presented at the 13th European Conference on Applied Superconductivity, EUCAS 2017, 17-21 September 2017, Geneva, Switzerland

Inductance of superconducting thin-film inductors and structures with linewidth down to 250 nm has been experimentally evaluated. The inductors include various striplines and microstrips, their 90-degree bends and meanders, interlayer vias, etc., typically used in superconducting digital circuits. The circuits have been fabricated by a fully planarized process with 8 niobium layers, developed at MIT Lincoln Laboratory for very-large-scale superconducting integrated circuits. Excellent run-to-run reproducibility and inductance uniformity of better than 1% across 200-mm wafers have been found. It has been found that the inductance per unit length of stripline and microstrip line inductors continues to grow as the inductor linewidth is reduced deep into the submicron range to the widths comparable to the film thickness and magnetic field penetration depth. It is shown that the linewidth reduction does not lead to widening of the parameter spread due to diminishing sensitivity of the inductance to the linewidth and dielectric thickness. The experimental results were compared with numeric inductance extraction using commercial software and freeware, and a good agreement was found for 3-D inductance extractors. Methods of further miniaturization of circuit inductors for achieving circuit densities > 10^6 Josephson junctions per cm^2 are discussed., 5 pages, 7 figures, 31 references. Presented at Applied Superconductivity Conference, ASC 2014, Charlotte, NC, USA, August 10-15, 2014

A fabrication process for Nb/Al-AlOx/Nb Josephson junctions (JJs) with sizes down to 200 nm has been developed on a 200-mm-wafer tool set typical for CMOS foundry. This process is the core of several nodes of a roadmap for fully-planarized fabrication processes for superconductor integrated circuits with 4, 8, and 10 niobium layers developed at MIT Lincoln Laboratory. The process utilizes 248 nm photolithography, anodization, high-density plasma etching, and chemical mechanical polishing (CMP) for planarization of SiO$_2$ interlayer dielectric. JJ electric properties and statistics such as on-chip and wafer spreads of critical current, $I_c$, normal-state conductance, $G_N$, and run-to-run reproducibility have been measured on 200-mm wafers over a broad range of JJ diameters from 200 nm to 1500 nm and critical current densities, $J_c$, from 10 kA/$cm^2$ to 50 kA/$cm^2$ where the JJs become self-shunted. Diffraction-limited photolithography of JJs is discussed. A relationship between JJ mask size, JJ size on wafer, and the minimum printable size for coherent and partially coherent illumination has been worked out. The $G_N$ and $I_c$ spreads obtained have been found to be mainly caused by variations of the JJ areas and agree with the model accounting for an enhancement of mask errors near the diffraction-limited minimum printable size of JJs. $I_c$ and $G_N$ spreads from 0.8% to 3% have been obtained for JJs with sizes from 1500 nm down to 500 nm. The spreads increase to about 8% for 200-nm JJs. Prospects for circuit densities > $10^6$ JJ/$cm^2$ and 193-nm photolithography for JJ definition are discussed.

Superconducting single-flux-quantum-based (SFQ) digital integrated circuits (ICs) are a promising candidate for high-speed and ultralow energy dissipation computing systems. Circuits based on several versions of SFQ-type logic, RQL, and AQFP logic have been demonstrated with complexities reaching up to a few tens of thousands of gates. Packaging many superconducting ICs using microbump (15µm or less) technology and performing high throughput, nearly lossless data transfer between various superconducting and/or CMOS chips are highly desirable for a hybrid superconducting computer architecture, but this density has not yet been demonstrated. An efficient way to achieve this goal is to couple the chips through a passive superconductive multichip module (S-MCM) that distributes information between integrated circuits utilizing lossless superconducting transmission lines. Here we show implementation of such a superconducting base using well-defined impedance lines to couple multiple ICs to enable a cryogenic integration approach for possible future hybrid superconducting computing systems. The use of indium-based microbumps to form interconnects between an S-MCM and superconducting ICs, and its electrical performance, are discussed. Optimized microbumps were used to fabricate interconnections on a large S-MCM by using thermocompression(TC) bonding. From 17200 to 68800 microbumps fabricated in a 5 mm × 5 mm active area of an S-MCM, having pitches ranging from 35 µm to 15 µm, were bonded with a superconducting IC to create a daisy chain structure. In addition, a large active area (10 mm × 10 mm) flip-chip having continuous niobium daisy chains with up to 77,500 bumps with 15 µm bump diameter and 35 µm pitch was also demonstrated. As a case study, an optimized microbump interconnect construction for attaching 16 superconducting chips with a large 32 mm × 32 mm superconducting base was fabricated and tested at room temperature and 4.2 K to study the structural and electrical integrity. Josephson junctions and niobium lines on integrated superconducting chips and the superconducting base maintained their I-V characteristics, which allows the design of building blocks for a superconducting computing system.

We are developing a superconductor electronics fabrication process with up to nine planarized superconducting layers, stackable stud vias, self-shunted Nb/AlOx-Al/Nb Josephson junctions, and one layer of MoNx kinetic inductors. The minimum feature size of resistors and inductors in the process is 250 nm. We present data on the mutual inductance of Nb stripline and microstrip inductors with linewidth and spacing from 250 nm to 1 {\mu}m made on the same or adjacent Nb layers, as well as the data on the linewidth and resistance uniformity., Comment: Extended Abstract: 3 pages, 4 figures, 1 Table, 9 references. 16th International Superconductive Electronics Conference, ISEC 2017, 12-16 June 2017, Sorrento, Italy

Coherent circuits based on superconducting elements hold tremendous promise for the practical implementation of quantum information technology: advanced computation, cryptography, and hardware simulation of complex materials systems are envisioned applications. Such circuits are essentially engineered atoms with level transitions in the 4–8 GHz regime; as such “read” and “write” operations are performed with the aid of fast microwave pulses and low-noise amplifiers, respectively. Recent advances in cavity-based superconducting parametric amplifiers have enabled real-time measurement and feedback in one and two qubits. We demonstrate a novel Josephson junction transmission-line based traveling-wave amplifier which employs sub-wavelength phase matching resonators to achieve high gain, several GHz of bandwidth, and near quantum-noise limited performance. Such devices will enable multiplexed qubit readout in integrated architectures comprised of a variety of microwave frequency analog and digital superconducting technologies: signal sources, multiplexers, ADCs, DACs, mixers, and amplifiers.

Stringing together a powerful amplifier Amplifying microwave signals with high gain and across a broad range of frequencies is crucial in solid-state quantum information processing (QIP). Achieving broadband operation is especially tricky. Macklin et al. engineered an amplifier that contains a long chain of so-called Josephson junctions (see the Perspective by Cleland). The amplifier exhibited high gain over a gigahertz-sized bandwidth and was able to perform high-fidelity qubit readout. Because the amplifier will be capable of reading out as many as 20 qubits simultaneously, it may help to scale up QIP protocols. Science , this issue p. 307 ; see also p. 280

We review the salient features of two advanced nodes of an 8-Nb-layer fully planarized process developed recently at MIT Lincoln Laboratory for fabricating Single Flux Quantum(SFQ) digital circuits with very large scale integration on 200-mm wafers: the SFQ4ee and SFQ5ee nodes, where 'ee' denotes the process is tuned for energy efficient SFQ circuits. The former has eight superconducting layers with 0.5 {\mu}m minimum feature size and a 2 {\Omega}/sq Mo layer for circuit resistors. The latter has nine superconducting layers: eight Nb wiring layers with the minimum feature size of 350 nm and a thin superconducting MoNx layer (Tc ~ 7.5 K) with high kinetic inductance (about 8 pH/sq) for forming compact inductors. A nonsuperconducting (Tc < 2 K) MoNx layer with lower nitrogen content is used for 6 {\Omega}/sq planar resistors for shunting and biasing of Josephson junctions. Another resistive layer is added to form interlayer, sandwich-type resistors of m{\Omega} range for releasing unwanted flux quanta from superconducting loops of logic cells. Both process nodes use Au/Pt/Ti contact metallization for chip packaging. The technology utilizes one layer of Nb/AlOx-Al/Nb JJs with critical current density, Jc of 100 {\mu}A/{\mu}m^2 and minimum diameter of 700 nm. Circuit patterns are defined by 248-nm photolithography and high density plasma etching. All circuit layers are fully planarized using chemical mechanical planarization (CMP) of SiO2 interlayer dielectric. The following results and topics are presented and discussed: the effect of surface topography under the JJs on the their properties and repeatability, critical current and Jc targeting, effect of hydrogen dissolved in Nb, MoNx properties for the resistor layer and for high kinetic inductance layer, technology of m{\Omega}-range resistors., Comment: 10 pages, 12 figures, 1 table, 27 references. The paper was presented on September 8, 2015 at the 12th European Conference on Applied Superconductivity, EUCAS 2015, 6-10 September 2015, Lyon, France, IEEE Transaction on Applied Superconductivity, 2016

The spectral density S(Φ)(f) = A(2)/(f/1 Hz)(α) of magnetic flux noise in ten dc superconducting quantum interference devices (SQUIDs) with systematically varied geometries shows that α increases as the temperature is lowered; in so doing, each spectrum pivots about a nearly constant frequency. The mean-square flux noise, inferred by integrating the power spectra, grows rapidly with temperature and at a given temperature is approximately independent of the outer dimension of a given SQUID. These results are incompatible with a model based on the random reversal of independent, surface spins.

Superconducting coplanar waveguide (SCPW) resonators have a wide range of applications due to the combination of their planar geometry and high quality factors relative to normal metals. However, their performance is sensitive to both the details of their geometry and the materials and processes that are used in their fabrication. In this paper, we study the dependence of SCPW resonator performance on materials and geometry as a function of temperature and excitation power. We measure quality factors greater than $2\times10^6$ at high excitation power and $6\times10^5$ at a power comparable to that generated by a single microwave photon circulating in the resonator. We examine the limits to the high excitation power performance of the resonators and find it to be consistent with a model of radiation loss. We further observe that while in all cases the quality factors are degraded as the temperature and power are reduced due to dielectric loss, the size of this effect is dependent on resonator materials and geometry. Finally, we demonstrate that the dielectric loss can be controlled in principle using a separate excitation near the resonance frequencies of the resonator., Comment: Replacing original version. Changes made based on referee comments. Fixed typo in equation (3) and added appendix

In this work, we modified our wafer-scale 3D integration technique, originally developed for Si, to hybridize InP-based image sensor arrays with Si readout circuits. InGaAs image arrays based on the InGaAs layer grown on InP substrates were fabricated in the same processing line as silicon-on-insulator (SOI) readout circuits. The finished 150-mm-diameter InP wafer was then directly bonded to the SOI wafer and interconnected to the Si readout circuits by 3D vias. A 1024 × 1024 diode array with 8-µm pixel size is demonstrated. This work shows the wafer-scale 3D integration of a compound semiconductor with Si.

This paper discusses on demonstration of charge-coupled devices in fully depleted SOI. CCDs implemented in FDSOI are expected to operate up to higher speeds than conventional bulk surface-channel CCDs. While FDSOI CCDs retain the high linearity and charge storage density of surface-channel CCDs, the buried oxide (BOX) layer allows strong fringing electric fields to penetrate beneath the gates and accelerate the transfer of charge from gate to gate. The simulation results illustrate the speed improvement with increasing BOX thickness. The improvement saturates when the BOX thickness becomes comparable to the gate length.

A theory of monopolar space-charge-limited currents in insulator with exponential energy distribution of capture centers is developed without making any of the usual assumptions. In particular, the finite temperature form of the Fermi-Dirac statistics is incorporated in the exact parametric solution of the problem. It is shown that the exact solution can be accurately represented using newly developed closed form analytical approximations. A comparison with traditional models shows that their areas of validity are quite limited. In particular, in a number of important cases the celebrated power law equation of the current-voltage characteristic is not a valid approximation of the exact result.

We report the results of an experimental investigation of the temperature dependence of electron trapping and dielectric breakdown in MOS devices operated in the 77–400 K temperature range. In contrast to avalanche or hot-electron injection investigated previously, the trapping of electrons in the regime of tunneling injection is suppressed at low temperatures. This result is related to the retardation of the time dependent dielectric breakdown observed for the low temperature operation of MOS devices. It is shown that both the failure rate and the temperature dependence of the time dependent dielectric breakdown is reduced for the low temperature operation. If Arrhenius law is used to describe the maximum number of carriers which can be injected into SiO2 prior to dielectric breakdown, then for temperature between 77 and 200 K the activation energy is reduced by approximately an order of magnitude as compared to its room temperature value.

A two‐step process for oxidation of silicon results in an improvement in thin silicon dioxide breakdown voltage distributions. This conclusion, previously demonstrated for approximately 8‐nm‐thick oxides, is shown to be valid for thicker oxides as well. However, no information was previously available concerning the trapping characteristics of gate insulators formed using the two‐step oxidation process. In this work, we used the substrate hot electron effect to investigate the trapping characteristics of new insulators. Based on the degradation rate of both threshold voltage and linear transconductance of metal‐oxide‐semiconductor transistors, we conclude that the two‐step oxidation process reduces the rate of substrate hot carrier induced degradation, in addition to improving the gate insulator integrity. We also observed a strong correlation between the degradation in linear transconductance and threshold voltage. This correlation is explained by the generation of, and trapping at, interface states and bulk oxide traps. Under our experimental conditions, the interface state density increases sublinearly with the number of electrons injected into the gate insulator. Investigation of the trapping kinetics indicates the presence of two trap species, only one of which influences the degradation in linear transconductance.