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Background: Depending on the geographical area and socioeconomic state of the population, numerous diseases can cause visual impairment and blindness in children. Blindness in children in underdeveloped nations is typically caused by illnesses that result in corneal scarring such as vitamin A deficiency, measles infection, neonatal conjunctivitis, and dangerous traditional eye medications. Cataract, retinopathy of prematurity, genetic disorders, and congenital anomalies are the most common causes elsewhere. This issue is complicated by a lack of information about eye care and utilization of eye treatments. Methods: For this study, an evaluative technique was applied. The data was collected using a one-group pre-test and post-test design. The organized teaching programme on prevention of eye problems in children was the study's independent variable, while the knowledge level of mothers on prevention of eye problems was the dependent variable. A structured interview schedule was utilized to collect data from 100 mothers who were recruited using the purposive sample technique.Results: In the pre-test, the mean percentage of total knowledge was 56.35, with a standard deviation of 2.37. The mean percentage of total knowledge in the posttest was 75.83, with a standard deviation of 1.37. The obtained t value of 24.70 was larger than the table value of 2.66 and it was judged to be significant at the threshold of 0.01.Conclusions: Study demonstrated that the organized education programme was successful in raising mothers' awareness about the prevention of eye disorders in children.

The key player in the multi-clock domain system is the synchronizer. This synchronizer suffers from the effect of metastability and results in the failure of the circuit. Prevention of the synchronizer from the metastability is feasible. Metastable state occurs whenever there is a violation of setup and hold time i.e., uncontrolled and unpredictable change in data within setup and hold time window. In this paper, we proposed a new architecture of the synchronizer. It detects any transitions in data signal within metastability window. The closed loop gains of the cross-coupled inverter are controlled by the external signal. This signal will ensure the correct state of the synchronizer. The additional part of the latch comes into action when this ambiguity occurs. The correctness of the circuit functionality is verified using HSPICE and Tanner EDA at the 32nm technology.

The many applications consist of multiple clock domains. There is data transfer between these clock domain systems. Due to different frequencies between sender and receiver there is data loss. Synchronizer is used for data synchronization. Synchronizer is having non-zero probability of failure in Globally Asynchronous Locally synchronous System on Chip. Synchronizer plays very crucial role in determining the reliability of system. The synchronizer is having parameters. These parameters associated with synchronizer are clock, data rate and timing window (setup and hold time). But in practice the synchronizer suffers from metastability as data changes in timing window due to which synchronizer failure occurs. As the metastability occurs we cannot predict the correct level of output. Metastability states are common in digital circuits, and synchronizers are must to protect their fatal effects. Originally, they were required when reading an asynchronous input. Now, with multiple clock domains on the same chip, synchronizers are required when on-chip data crosses the clock domain boundaries. The proposed architecture is modeled with verilog and simulated with Xilinx ISE design suit 13.1 and Quartus II 10.1. Analog behavior is studied by using Tanner 13.1. The probability of failure is analyzed and simulated. It has been found that it is affected by clock rate.

Interconnect fabric requires easy integration of computational block operating with unrelated clocks. This paper presents asynchronous interconnect with ternary tree asynchronous network for Globally Asynchronous Locally Synchronous (GALS) system-on-chip (SOC). Here architecture is proposed for interconnection with ternary tree asynchronous network where ratio of number NOC design unit and number of router is 4:1,6:2, 8:3,10:4 etc .It is scalable for any number of NOC design unit. It offers an easy integration of different clock domain with low communication overhead .NOC design unit for GALS ‘SOC is formulated by wrapping synchronous module with input port along with input port controller, output port along with output port controller and local clock generator. It creates the interface between synchronous to asynchronous and asynchronous to synchronous. For this purpose four port asynchronous routers is designed with routing element and output arbitration and buffering with micro-pipeline. This interconnect fabric minimizes silicon area, minimize Latency and maximize throughput. Here functional model is made for TTAN and application MPEG4 is mapped on the Network .Desired traffic pattern is generated and performance of the network is evaluated. Significant improvement in the network performance parameter has been observed.&nbsp

Asynchronous design offers an attractive solution to overcome the problems faced by Networks-on-Chip (NoC) designers such as timing constraints. GALS Asynchronous NoCs requires efficient calibrated clocking scheme which has minimum drift, independent of Process Voltage Temperature(PVT), use minimum static and dynamic power. Clocking scheme should enable smooth synchronization among different clock domain. This paper first presents novel data dependent Pausible clocking scheme with Phase lock loop calibration. It calibrate for phase alignment. Local Clock is calibrated with reference clock generated from reference clock source with PLL mode for the desired frequency which is set with dealylined. This aligned local clock will use for clocking of synchronous module which is wrapped with asynchronous wrapper. It helps in avoiding metastability during crossing of data from one clock domain to another clock domain. Here we present the Petri net models of the Globally Asynchronous and Locally Synchronous(GALS) architectures for speed independent (SI). The models are feed into Petrify to produce logic equations for gate level implementation of asynchronous circuit. The synchronous and asynchronous circuits are implemented on technology of saed90nm provided with Synopsys university program. Simulation is carried on VCS of Synopsys and synthesis on design compiler.