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FPGAs are gaining popularity as the target of choice for the efficient implementation of Deep Neural Networks (DNNs) approaches. Modern SoCs with integrated FPGAs have low-power on-chip processors and sufficient interfaces to accommodate the most commonly deployed Internet of Things (IoT) devices. However, developing DNN hardware accelerators using integrated FPGAs remains a complicated task due to the complexity of reconfigurable computing and limited hardware resources on embedded devices. In addition, it is necessary to master High-Level Synthesis tools (HLS) and their hidden philosophy driving RTL design. This paper presents our Python framework to fully customize and automate the generation and deployment of FPGA-based DNN topologies for Edge Computing. Our framework environment, Jupyter Notebooks, allows users to customize their desired hardware DNN and its related applications on Xilinx’s Pynq boards. Subsequently, the framework automatically generates TCL (Tool Command Language) scripts driving HLS tools on the host server or cloud. Once the desired FPGA-based architecture is generated, the framework retrieves the bitstream to configure the FPGA. Therefore, the user can deploy this bitstream to accelerate any Python application that performs the same DNN model. The experimental results show that our framework can speed up 59.8× a 784-32-32-10 topology, while the power consumption is less than 0.266W.

Energy efficiency is a growing concern for modern computing, especially for HPC due to operational costs and the environmental impact, considering that processors have an important role in this energy consumption. In this work, we propose a methodology to find energy-optimal frequency and number of active cores to run single-node HPC applications using an application-agnostic power model of the architecture and an architecture-aware performance model of the application. We characterize the application performance using machine learning, specifically the “Support Vector Regression” algorithm. Besides that, the power consumption is estimated by modeling CMOS dynamic and static power without knowledge of the application. So, The energy-optimal configuration is estimated by minimizing the product these two models outcomes, the power model and the performance model. Then, the final model can be used to find better frequency and number of cores to aim energy efficiency application execution. Results were obtained for four PARSEC applications and, with five different inputs shows that the proposed approach used substantially less energy when compared to the DVFS governor, in best cases and worst cases.

Taking advantage of the growing number of cores in supercomputers to increase the scalability of parallel programs is an increasing challenge. Many advanced profiling tools have been developed to assist programmers in the process of analyzing data related to the execution of their program. Programmers can act upon the information generated by these data and make their programs reach higher performance levels. However, the information provided by profiling tools is generally designed to optimize the program for a specific execution environment, with a target number of cores and a target problem size. A code optimization driven towards scalability rather than specific performance requires the analysis of many distinct execution environments instead of details about a single environment. With the goal of providing more useful information for the analysis and optimization of code for parallel scalability, this work introduces the PaScal Viewer tool. It presents an novel and productive way to visualize scalability trends of parallel programs. It consists of four diagrams that offers visual support to identify parallel efficiency trends of the whole program, or parts of it, when running on scaling parallel environments with scaling problem sizes.