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A comprehensive study of the impact of Sn content on the Ni/GeSn phase sequence, the morphological and electrical properties evolution during the solid-state reaction (SSR) has been performed. The phase sequence was monitored by in-situ X-ray diffraction. These results were complemented by atomic force microscopy and sheet resistance measurements together with transmission electron microscopy imaging and energy-dispersive X-ray spectroscopy applied to specimens annealed both ex-situ and in-situ. The phase formation and Sn behavior during the solid-state reaction was followed. Sn segregation around grain boundaries hampered atom diffusion, delaying the growth of the Ni(GeSn) phase. In addition, a correlation between the Sn content and the morphological and electrical properties degradation has been observed.

Ni-based intermetallics are promising materials for forming efficient contacts in GeSn-based Si photonic devices. However, the role that Sn might have during the Ni/GeSn solid-state reaction (SSR) is not fully understood. A comprehensive analysis focused on Sn segregation during the Ni/GeSn SSR was carried out. In situ X-ray diffraction and cross-section transmission electron microscopy measurements coupled with energy-dispersive X-ray spectrometry and electron energy-loss spectroscopy atomic mappings were performed to follow the phase sequence, Sn distribution and segregation. The results showed that, during the SSR, Sn was incorporated into the intermetallic phases. Sn segregation happened first around the grain boundaries (GBs) and then towards the surface. Sn accumulation around GBs hampered atom diffusion, delaying the growth of the Ni(GeSn) phase. Higher thermal budgets will thus be mandatory for formation of contacts in high-Sn-content photonic devices, which could be detrimental for thermal stability.

International audience; The structural properties of CVD-grown (Si)GeSn heterostructures were assessed thanks to scanning transmission electron microscopy at the nanometer scale. Quantitative energy dispersive x-ray (EDX) spectroscopy together with precession electron diffraction and geometrical phase analysis (GPA) were performed to probe the chemical and structural properties of the different layers. Results presented in this paper demonstrated the advantages of a multilayer structure, with successive layers grown at decreasing temperatures in order to gradually accommodate the in-plane lattice parameter and incorporate more and more Sn into the stack. It was shown how the GeSn emissive layer could be manufactured with low plastic deformation and a high relaxation rate, necessary for better light emission performances. SiGeSn alloys used as confinement barriers around the emissive layer were also investigated. For such thin layers, we showed the importance of the starting lattice parameter (SLP) prior to the growth on their composition. Indeed, higher SLPs resulted, for the very same process conditions, into higher Sn contents and lower Si contents. The interest in combining EDX, which was accurate enough to detect slight chemical concentration variations, and GPA, for local strain analyses, was clearly demonstrated. Present results will be very useful to predict and control the bandgap and structural quality of (Si)GeSn materials and, in turn, device properties.

International audience; Ultraviolet Nanosecond Laser Annealing (UV-NLA) was performed on 30 nm-thick Si0.8Ge0.2 epitaxial layers. The various regimes encountered, depending on the melt depth after single pulse UV-NLA, are described and discussed in this paper. Energy densities around 2.00 J/cm(2) and above led to the formation of pseudomorphic layers with a strong Ge redistribution. Starting from uniform Si0.8Ge0.2 layers, Ge segregation toward the surface resulted in the formation of a Ge-rich surface layer with up to 55 at.% Ge for 2.00 J/cm(2). Such pseudomorphic SiGe layers with a graded composition and a Ge-rich surface may find promising applications such as contact resistance lowering in doped layers.

During the fabrication of a MOS-HEMT, the plasma-etching steps are critical because they can damage the GaN materials and lead to electrical degradation effects. To address these limitations, we studied the influence of plasma parameters on electrical degradation in an AlGaN/GaN heterostructure. In this work, the modifications induced by bias-voltage applied during the SiN capping layer opening are investigated. Physical (XRD, XRR, AFM and TEM) and chemical (XPS) characterizations have been performed to have a better understanding this plasma parameter on GaN damage. These results are correlated with Rsheet measurements to evaluate the electrical degradation in the heterostructure. Finally, degradation mechanisms and recommendation have been proposed to improve the plasma etching process.

In the context of the development of silicon photonics, various Ti- and Ni-based alloyed metallizations have been investigated for the purpose of forming low resistivity and Si CMOS-compatible contacts to n-InP. The innovative Ni2P metallization combined with an in situ Ar+ preclean represents the most suitable available solution for the formation of ohmic contacts with a specific contact resistivity as low as $4.3 \times 10^{-6}~\Omega ^{2}$ on such a semiconductor. The latter additionally presents the advantage of being stable at least up to 350 °C and could therefore withstand additional integration processes conducted at this temperature.

The family of III-Nitride semiconductors has been under intensive research for almost 30 years and has revolutionized lighting applications at the dawn of the 21st century. However, besides the developments and applications achieved, nitride alloys continue to fuel the quest for novel materials and applications. We report on the synthesis of a new nitride-based compound by using annealing of AlN heteroepitaxial layers under a Si-atmosphere at temperatures between 1350 °C and 1550 °C. The structure and stoichiometry of this compound are investigated by high resolution transmission electron microscopy (TEM) techniques and energy dispersive X-Ray (EDX) spectroscopy. Results are supported by density functional theory (DFT) calculations. The identified structure is a derivative of the parent wurtzite AlN crystal where the anion sublattice is fully occupied by N atoms and the cation sublattice is the stacking of 2 different planes along : The first one exhibits a ×3 periodicity along with 1/3 of the sites being vacant. The rest of the sites in the cation sublattice are occupied by an equal number of Si and Al atoms. Assuming a semiconducting alloy, a range of stoichiometries is proposed, Al5+αSi5+δN12 with α being between −2/3 and 1/4 and δ between 0 and 3/4.

GeSn material has been envisioned as an alternative to the complex integration of III-V lasers on Silicon (Si) for photonic applications [1]. GeSn heterostructures with 16 at.% of Sn were demonstrated [2]. Increasing the Sn at.% is of high interest in these devices. Additionally, high quality contacts are needed to achieve electrical pumping, for which Nickel intermetallics were proposed. Indeed, Ni(GeSn) exhibit low temperatures formation and low resistances values. Currently, it is not entirely known how Sn incorporates in Ni-GeSn phases. Sn might: (i) be soluble in the phase, (ii) segregate, and/or (iii) form Ni-Sn alloys [3,4]. The Sn content is otherwise expected to impact different aspects of the phase sequence [5], as well as morphological and electrical properties. We propose a comprehensive study of the Ni-GeSn intermetallics focusing on Sn segregation and its impact on phase stability. 60 nm-thick Ge and Ge1-xSnx layers with 6, 10 and 15 at.% of Sn, were epitaxially grown on Ge-buffered Si (100) substrates. Surface preparation was performed with 1% diluted HF. Then, 10 nm of Ni were deposited by physical vapor deposition and capped with 7 nm of TiN. The Ni-Ge1-xSnx phase sequence and crystalline evolution were monitored by in-situ X-ray diffraction (XRD). Cross-section transmission electron microscopy (XTEM) measurements coupled with energy-dispersive X-ray spectrometry (EDS) and electron energy-loss spectroscopy (EELS) atomic maps were acquired to follow Sn distribution and segregation. Figure 1 shows the phase sequence of the Ni-Ge0.90Sn0.10 system. The growth was sequential. The first phase appearing was the Ni5(GeSn)3 phase. It was followed by the growth of the Ni(GeSn) phase [5 – 7]. EDS profiles confirmed that Sn was incorporated in both the Ni-rich and Ni(GeSn) phases. Similar phase sequences were obtained for all systems, from a straightforward comparison of in-situ XRD patterns. The threshold temperature above which the Ni-rich phase disappeared (and the less resistive Ni(GeSn) phase appeared) increased with Sn content: from 180 °C up to 235 °C and 245 °C for 0, 6 and 10 at.% of Sn, respectively (Figure 2). A dependence of the phase transition on the Sn content in the layers was evidenced. This trend was not observed for the Ni-Ge0.85Sn0.15 system due to Sn segregation at lower temperatures. XTEM analyses coupled with EDS and EELS (Figure 3) enabled us to track Sn segregation. Flat and continuous layers were obtained from the as-deposited state up to 350 °C. At 350 °C, Sn segregation started. It happened first around grain boundaries (GB) and then near the surface. At 400 °C, the Ni(GeSn) layers lost their continuity due to grain boundary grooving and agglomeration (confirmed by atomic force microscopy (AFM)). Grains were mainly composed of Ni and Ge atoms. Sn was predominantly localized at GB and close to the surface. At 550 °C, Sn coming from the intermetallic and from the GeSn thick layers underneath, completely migrated towards the surface. Figure 4 presents a Sn behavior schematic summary. Sn distribution and segregation impacted the Ni-Ge(Sn) phase sequences. Due to the role GB have on atomic transport, Sn segregation in those highly energetic areas might have reduced atoms mobility. Indeed, GB normally offer preferential paths, with enhanced atomic mobility [8]. GBs modified/saturated by Sn, can reduce the diffusion rate for phase formation. We thus believe that Sn acts as a “stuffed barrier”, hampering two-way atomic traffic. The higher the Sn content, the greater the hampering effect is, which slowed down Ni diffusion and delayed phase formation. We showed that Sn segregation in Ni-GeSn layers resulted in higher thermal budgets needed to obtain the less resistive phase (Ni(GeSn)) and have proper electrical contacts. Those thermal budgets could be detrimental for layers’ stability. In-situ TEM-EDS, AFM and sheet resistance results will also be presented, together with alternative solutions to delay Sn segregation. Acknowledgements: We would like to thank Virginie Loup for the wet surface treatment. This work was supported by the French National Research Agency (ANR) under the “Investissements d’avenir” programs: ANR-10-AIRT-0005 (IRT-NANOELEC), ANR-10-EQPX-0030 (EQUIPEX-FDSOI-11) and by the CEA DSM-DRT Phare project “Photonics”. References: [1]S. Wirths et al. Nat. Photonics, 9, 88-92, (2015). [2]J. Chretien et al. ACS Photonics, 6, 2462-2469, (2019). [3]J. Demeulemeester et al. Appl. Phys. Lett., 99 (21), 211905, (2011). [4]Y. Liu et al. ECS Solid State Letters, 3 (2), 11-13, (2014). [5]A. Quintero et al., J. Appl. Cryst., 53(3), (2020). [6]A. Quintero et al., J. Appl. Cryst., 51, 1133-1140 , (2018). [7]A. Quintero et al., Mater. Sci. Semicond. Process., 108, 104890, (2020). [8]M. A. Nicolet et al. Thin Film Solid. 52 (3), 415-443, (1978). Figure 1

For the first time, a comprehensive study going from the integration of 3D stacked nanosheets Gate-All-Around (GAA) MOSFET devices to SPICE modeling is proposed. Devices have been successfully fabricated on SOI substrates using a replacement high- $\kappa$ metal gate process and self-aligned-contacts. Back-biasing is herein efficiently used to highlight a drastic improvement of electrostatics in the upper GAA Si channels. Advanced electrical characterization of these devices enabled us to calibrate a new version of physical compact model (LETI-NSP) in order to assess the performance of ring oscillators for different configurations of GAA FETs integrating up to 8 vertically stacked Si channels.

Indium phosphide (InP) and gallium arsenide (GaAs) 100 mm wafers were bonded by direct wafer bonding in a cleanroom environment. Unexpected high bow values measured at room temperature after different thermal annealings are the focus of this study. Various experiments such as in situ bow measurements, surface XPS characterizations and TEM cross section observations highlight the key mechanisms that evolve with temperature. Over 200 °C, gallium oxide is formed at the bonded interface due to the presence of water that is trapped at the InP/GaAs interface during the hydrophilic bonding. These results allow us to explain the heterostructure debonding/re-bonding behavior.

session 32: Process and Manufacturing Technology (32.2); International audience; For the first time, a low temperature (LT) FinFET process is demonstrated, using Solid Phase Epitaxy Regrowth (SPER), gate last integration and Self Aligned Contact (SAC). The LT devices exhibit performances close to those of the High Temperature Process Of Reference (HT POR). Several techniques of SPER doping are investigated and an innovative Double SPER (DSPER) process using two amorphization/recrystallization steps, is demonstrated. This DSPER process has the advantage of doping the bulk of the S/D junctions. This work opens the door to the fabrication of high-performance LT FinFETs for 3D sequential integration.

Forming and breaking a nanometer-sized conductive area are commonly accepted as the physical phenomenon involved in the switching mechanism of oxide resistive random access memories (OxRRAM). This study investigates a state-of-the-art OxRRAM device by in-situ transmission electron microscopy (TEM). Combining high spatial resolution obtained with a very small probe scanned over the area of interest of the sample and chemical analyses with electron energy loss spectroscopy, the local chemical state of the device can be compared before and after applying an electrical bias. This in-situ approach allows simultaneous TEM observation and memory cell operation. After the in-situ forming, a filamentary migration of titanium within the dielectric hafnium dioxide layer has been evidenced. This migration may be at the origin of the conductive path responsible for the low and high resistive states of the memory.

session: Monolithic 3D 3; International audience; This work investigates the possibility to reduce the Solid Phase Epitaxy Regrowth (SPER) temperature for dopant activation needed in 3D sequential integration. The electrical results obtained on 28nm FDSOI devices show that 500°C SPER can yield similar performance to that of 600°C SPER and 1050°C spike anneal. This paper highlights the advantages of using a -oriented channel and tilted implantation to successfully reduce the SPER thermal budget. It also confirms that the channel can be used as a seed for the recrystallization. The analysis takes into account the SPER rate dependence on temperature, crystalline orientation, dopant type and dopant concentration.

For the first time the thermal stability of a new fluorine-free (F-free) W barrier coupled with W interconnections enabling 22% line 1 resistance improvement is evaluated in view of 3D VLSI integration. Integrated with ULK, no resistance nor lateral capacitance degradation is observed up to 550°C 5h while preserving good reliability. For additional thermal stability a TEOS/W stability is demonstrated up to 600°C 2h. Both types of interconnection stacks have been successfully integrated on devices with 28nm design rules and show similar performance for MOSFETs and Ring Oscillators (RO) as compared to the ULK/Cu stack. Finally, iBEOL guidelines are given at the end in view of 3D sequential integration.

This work provides breakthroughs in key technological modules for high performance and reliable 3D Sequential Integration with intermediate BEOL (iBEOL) in-between tiers. We demonstrate that (i) a high-quality solid phase epitaxy process is possible at 500°C, (ii) TiN native oxide removal prior to poly deposition leads to an improvement in gate stack reliability below 525°C and (iii) state-of-the-art SiOCH ULK in iBEOL is reliable up to 550°C 5h with W metal lines. A process integration is thus proposed to match the process windows of bottom layers (bottom FET and iBEOL) stability and top devices performance and reliability, opening perspectives for a wide range of applications and technologies using 3D Sequential Integration.

In this paper we present the impact of Sb doping of the GeS2 electrolyte in W/GeS2/Ag based conductive bridge random access memory (CBRAM) on the memory performance. In particular, the CBRAM resistance window, RON and ROFF values versus programming current, power consumption and reliability are analyzed in depth. We demonstrated that the Sb concentration governs the optimal operating conditions. In particular, high Sb doping allows low programming current operation (suitable for low power applications), while low Sb content improves the ROFF/RON ratio (needed in particular for nonvolatile field-programmable gate array applications). Finally, we observed that the high temperature retention could be improved by increasing the Sb doping. This result was interpreted by means of ab initio calculations, indicating that Sb reduces the dissolution rate of the Ag-based conductive filament in the electrolyte.

Short-gate length epitaxial Si1-xGex/Si multi-(core/shell) p-type nanowire (NW) transistors with high-permittivity dielectric and metal gate were fabricated and their electrical properties examined. Silicon NWs were first of all patterned in ultrathin silicon-on-insulator wafers by lithography and etching. Selective epitaxial growth of Si0.7Ge0.3/Si or Si0.7Ge0.3/Si/Si0.7Ge0.3/Si shells was then performed around the Si NW core. Electrical transport measurements showed a hole mobility improvement up to 100% in Si0.7Ge0.3/Si/Si0.7Ge0.3/Si core/shell NWs (70% in wide planar devices) compared with p-type Si reference field effect transistors (FETs). Finally, a drive current enhancement of 60% compared with reference Si-channel devices was evidenced in multi-(core/shell) p-FET NWs scaled down to 15-nm gate length.

Here, we report for the first time that electrodeposited CuSCN nanowires (NWs) could be successfully used as a new hole transporting layer (HTL) in a conventional polymer solar cell (PSC) with a poly[ N -9′-heptadecanyl-2,7-carbazole-alt-5,5-(4′,7′-di-2-thienyl-2′,1′,3′-benzothiadiazole)]:[6,6]-phenyl-C 71 -butyric acid methyl ester (PCDTBT:PC 70 BM) blend as an active layer. An efficient PSC with 5.1% power conversion efficiency for 28 mm 2 active surface area is fabricated. The performances of the PSCs prepared with electrodeposited CuSCN thin films and nanowires are compared and the obtained results clearly show that the nanostructuring of the HTL leads to an efficient hole extraction. The influence of the HTL thickness on the device performances was studied and it has been found that the thickness of the CuSCN nanowire array should not exceed the active layer thickness in order to keep high performances. An extraordinary high open circuit voltage (>900 mV) and a fill factor about 60% were measured. It is shown that the electrodeposited CuSCN thin films and NWs could be directly used in the polymer solar cells without any subsequent annealing process, which is a crucial point for the reduction of the device costs.

In this paper, we show that performances of Ge2Sb2Te5-based phase-change memory (PCM) cells can be improved by the insertion of a thin HfO2 interfacial layer between the phase-change material and the tungsten plug. Significant reduction of the RESET and SET currents and of the energy required to switch the PCM cells are demonstrated. In addition, compared with pure GST reference cells, the presence of the HfO2 layer leads to an enhanced endurance (>108 cycles) and an improved data-retention (ten years at 172°C). Using cross-sectional TEM-Energy Dispersive X-Ray (EDX) analyses and technology computer-aided design simulations, the decreases of the programming currents and energy are explained through the reduction of the PCM cell active area, due to the creation of conductive paths in the HfO2 layer during the initial forming procedure. Electrical measurements and modeling of the forming procedure indicate that the size of the conductive paths is controlled by the maximum current flowing through the PCM cells during the current overshoot of the forming procedure.

M.Casse, S. Barraud, R. Coquand, M. Koyama, D. Cooper, C. Vizioz, C. Comboroure, P. Perreau, V. Maffini-Alvaro, C. Tabone, L. Tosti, S. Barnola, V. Delaye, F. Aussenac, Ghibaudo, H.Iwai, G. Reimbold 1 CEA-Leti, MINATEC Campus, 17 rue des Martyrs, 38054 Grenoble, France 2 STMicroelectronics, 850 rue Jean Monnet, 38926 Crolles, France 3 IMEP-LAHC, INPG-MINATEC, 3 parvis Louis Neel, 38016 Grenoble, France 4 Frontier Research Center, Tokyo Institute of Technology, 4259 Nagatsuta, Midori-ku, Yokohama, Japan email: mikael.casse @cea.fr

While significant research effort on various planar approaches, the 3D vertical IC stacking is undoubtedly gaining increasing momentum as a leading contender in the challenge to meet performance, cost, and size demands through this decade and beyond. The Smart CutTM technology allowing the stack of very thin layers with direct bonding is one of the emerging technologies in this field. In this paper, the Smart CutTM technology using low temperature metal direct bonding (allowing direct vertical integration) is demonstrated.

Two approaches have been compared for the low temperature epitaxy of thick, partially relaxed GeSn layers on top of Ge strain relaxed buffers. The benefit of using step-graded instead of constant composition layers when targeting really high Sn contents (16%, here) was conclusively demonstrated. Digermane (Ge2H6) and tin-tetrachloride (SnCl4) were used as Ge and Sn precursors, respectively. The growth pressure (100 Torr) and the F(Ge2H6)/F(SnCl4) mass-flow ratio being constant, it was through a temperature lowering that the Sn concentration in the graded structure was increased. X-ray diffraction, atomic force microscopy and transmission electron microscopy were used to gain access to the Sn concentration, the strain state, the surface morphology and thicknesses of the heterostructures. Using a step-graded approach allowed us to gradually relax the strain in the GeSn layers. It helped us obtain high crystalline quality and avoid Sn segregation/precipitation for high Sn contents.

International audience; 3D sequential integration requires top FETs processed with a low thermal budget (500-600°C). In this work, high performance low temperature FDSOI devices are obtained thanks to the adapted extension first architecture and the introduction of mobility boosters (pMOS: SiGe 27% channel / SiGe:B 35% RSD and nMOS: SiC:P RSD). This first demonstration of n and p extension first FDSOI devices shows that low temperature activated device can match the performance of a device with state-of-the-art high temperature process (above 1000°C).

For the first time, a full 3D CMOS over CMOS CoolCube™ integration is demonstrated with a top level compatible with state of the art high performance FDSOI (Fully-Depleted Silicon On Insulator) process requirements such as High-k/metal gate or raised source and drain. Functional 3D inverters with either PMOS or NMOS on the top level are highlighted. Furthermore, Si layer transfer above a 28nm W Metal 1 level of an industrial short loop and the return in a front end environment is presented, confirming the industrial compatibility of CoolCube™ integration.

In 3D sequential integration, the top transistor thermal budget must be reduced to preserve bottom MOSFET performance. In order to relax this thermal budget limitation, the thermal stability of the bottom level must be increased, especially for the silicide. In that purpose, Ni0.9Co0.1 alloy is proposed to replace the current Ni0.85Pt0.15 silicide. For the first time, this Ni0.9Co0.1 salicide has been integrated on pMOS FDSOI transistors with state of the art process leading to performance improvements compared to the standard Ni0.85Pt0.15 salicide. In this study, the cobalt incorporation into the salicide has been investigated to enhance its thermal stability.

International audience; Direct metal bonding is a key technology for 3D integration that will allow semiconductor industry to go beyond predicted problems of future ICs. In this paper, for the first time, we show room temperature direct bonding of titanium layers on silicon wafers at atmospheric pressure and ambient air. Transmission electron microscopy and spreading scanning resistance microscopy are used to investigate bonding interface. Several physical mechanisms of titanium-titanium interface sealing during subsequent thermal annealing are observed and compared to copper and tungsten in terms of bonding mechanism and temperature dependence

Templates made of a thin single crystal GaAs layer on CTE-matched substrate (sapphire) have been realized using the Smart CutTM technology. These templates can withstand high processing temperatures thanks to the CTE matching between the GaAs thin film and its support, and therefore can be used for many applications since they require no specific restriction concerning thermal treatments. The GaAs templates have been compared to conventional bulk GaAs substrates. TEM images and XRD spectra show similar crystalline quality. AFM measurements show a similar surface microroughness. Photoluminescence of a AlGaAs double heterostructure grown by MOCVD on the GaAs template shows the same intensity as a reference structure on bulk GaAs. Therefore, the GaAs templates can replace GaAs bulk substrates in various domains such as photonics devices (solar cell, laser) or high frequency electronics.

In this paper, Silicon on Diamond (SOD) substrates were fabricated using the direct bonding process in two different technologies: the BESOI (Bonded and Etched-back SOI) and the Smart-Cut™ process. The polycrystalline diamond (C∗) film deposited by Chemical Vapor Deposition assisted by Microwave Plasma (MPCVD) was planarized by an innovative process which induces a significant decrease of the diamond surface roughness (1.2 nm for the 200 nm diamond layer). The planarization method as well as the entire SOD substrate process by the BESOI or the Smart-Cut™ technology are described in the paper. Cross sectional high-resolution transmission microscopy reveals the good quality of the future silicon channel on top of the thin diamond layer.

An original technique is used to induce a compressive strain in the channel of Fully Depleted (FD)SOI MOSFETs thanks to an Embedded Buried Nitride stressor. Strain measurements are performed by Grazing Incidence X-ray Diffraction (GIXRD) and compared to mechanical simulations. Both results are in agreement and prove that the strain level can achieve -0.6 percent (-780 MPa) in the channel of a transistor, depending on the active region geometry and the nitride properties (intrinsic strain and thickness). This technique is thus very promising in order to boost pMOSFETs on thin films.

The problematics of contacts optimization on Germanium MOSFETs suffers from a gap between fundamental studies and the structures obtained after full processing. The contact properties of metals such as Ti on Ge were so far mostly investigated on weakly n-doped samples under pure Thermionic Emission (TE) regime. In this paper, we detail Schottky Barrier Height (SBH) extractions based on contact resistance (Rco) measurements on highly n- and p-doped Ge, where the predominant tunnel current component results in ohmic behavior. We applied this methodology to our fully-processed GeOI samples with Ti-based contacts, yielding effective barriers of 0.32eV for electrons and 0.15eV for holes. The method provides a good physical understanding of the technological factors impacting their electrical properties, therefore enabling to define paths towards ohmic contact optimization in the context of device integration on GeOI.

The size reduction and increasing complexity of micro and nanotechnologies involve a need for advanced morphological and chemical characterization. Furthermore, reduced cycle time, low cost and high resolution imaging are required. To figure out this new challenge, a TEM and a full 200 and 300mm wafer FIB-SEM dual beam for sample preparation have been installed close to each other inside a process line cleanroom.Means to reach TEM and STEM atomic resolution inside cleanroom environment are presented. A sample preparation to observation flow of few hours is described. Impact of samples lift-out on wafers at different process levels is studied in the case of fully depleted silicon on insulator (FDSOI) CMOS technology. Electrical performances of adjacent transistors are measured and interpreted using SEM imaging of FIB crater areas.

International audience

As critical dimensions of interconnect structures in microelectronic devices decrease below 100nm, general electrical performance of copper lines is reduced, for example, resistivity is seen to increase. These phenomena are due to the limited size of copper grains within these narrow features. For this reason, control of the copper microstructure at this scale is a fundamental challenge for the fabrication of future circuits. This study focuses on copper grain growth mechanisms in narrow lines after annealing. Grain size measurements and electrical results are presented. Different grain growth regimes are observed, depending on both feature size and annealing temperature.

International audience; Combining Resistive RAM concept with Vertical NAND technology and design, Vertical RRAM (VRRAM) was recently proposed as a cost-effective and extensible technology for future mass data storage applications [1]. 3D RRAM based neural networks were also proposed to emulate the potentiation and depression of a synapse [2], but more complex circuits were not discussed. In previous works [3-4], various RRAM based neuromorphic circuits were proposed and investigated, using planar devices.

International audience; In this paper, we investigate in depth Forming, SET, and Retention of conductive-bridge random-access memory (CBRAM). A kinetic Monte Carlo model of the CBRAM has been developed considering ionic hopping and chemical reaction dynamics. Based on inputs from ab initio calculations and the physical properties of the materials, the model offers the simulation of both the Forming/SET and the Data Retention operations. It aims to create a bond between the physics at atomic level and the device behavior. From the model and experimental results obtained on decananometric devices, we propose an understanding of the physical mechanisms involved in the CBRAM operations. Using the consistent Forming/SET and Data Retention model, we obtained good agreement with the experimental data. Finally, the impact of each layer of the CBRAM on the Forming/SET behavior is decorrelated, allowing an optimization of the performance.

An automatic procedure for electron tomography is presented. This procedure is adapted for specimens that can be fashioned into a needle-shaped sample and has been evaluated on inorganic samples. It consists of self-adapting denoising, automatic and accurate alignment including detection and correction of tilt axis, and 3D reconstruction. We propose the exploitation of a large amount of information of an electron tomography acquisition to achieve robust and automatic mixed Poisson-Gaussian noise parameter estimation and denoising using undecimated wavelet transforms. The alignment is made by mixing three techniques, namely (i) cross-correlations between neighboring projections, (ii) common line algorithm to get a precise shift correction in the direction of the tilt axis and (iii) intermediate reconstructions to precisely determine the tilt axis and shift correction in the direction perpendicular to that axis. Mixing alignment techniques turns out to be very efficient and fast. Significant improvements are highlighted in both simulations and real data reconstructions of porous silicon in high angle annular dark field mode and agglomerated silver nanoparticles in incoherent bright field mode. 3D reconstructions obtained with minimal user-intervention present fewer artefacts and less noise, which permits easier and more reliable segmentation and quantitative analysis. After careful sample preparation and data acquisition, the denoising procedure, alignment and reconstruction can be achieved within an hour for a 3D volume of about a hundred million voxels, which is a step toward a more routine use of electron tomography.

Work function in Si1–xGex heterostructures with Ge content in the 6% to 49% range was studied with high energy resolution by combining Kelvin force microscopy and X-ray photoelectron emission microscopy. Although the two methods are based on distinct physical mechanisms, we show that both techniques give the same work function differences between each Si1–xGex layer, as small as 20 meV. To detect such small work function differences, we put in evidence the necessity of preparing the Si1–xGex sample surface with polishing, HF etching and Ar+ sputtering. Such surface preparation allows, in principle, to reduce the deleterious influence of surface states, coming for instance from carbon atoms or native oxide, on quantitative work function extraction. We show in this paper that even after such a sample surface preparation, a strong band bending can be present, which causes a contrast inversion on the surface of the material and yields an artificially lower surface work function with respect to theoretical val...

International audience; In this paper, we deeply investigate for the 1st time at our knowledge the impact of the CBRAM memory stack on the Forming, SET and RESET operations. Kinetic Monte Carlo simulations, based on inputs from ab-initio calculations and taking into account ionic hopping and chemical reaction dynamics are used to analyse experimental results obtained on decananometric devices. We propose guidelines to optimize the CBRAM stack, targeting Forming voltage reduction, improved trade-off between SET speed and disturb immunity (time voltage dilemma) and window margin increase (RESET efficiency).

We present for the first time sub-100nm poly-Silicon nanowire (poly-Si NW) based NEMS resonators for low cost cointegrated mass sensors on CMOS featuring excellent performance when compared to crystalline silicon. In particular, comparable quality factors (130 in the air, 3900 in vacuum) and frequency stabilities are demonstrated. The minimum measured Allan deviation of 7×10−7 leads to a mass resolution detection down to 100 zg (100×10−21 g). Moreover a novel method for in-line NW gauges factor (GF) extraction is proposed and used.

International audience; Precession electron diffraction is an efficient technique to measure strain in nanostructures by precessing the electron beam, while maintaining a few nanometre probe size. Here, we show that an advanced diffraction pattern treatment allows reproducible and precise strain measurements to be obtained using a default 512 x 512 DigiSTAR off-axis camera both in advanced or non-corrected transmission electron microscopes. This treatment consists in both projective geometry correction of diffraction pattern distortions and strain Delaunay triangulation based analysis. Precision in the strain measurement is improved and reached 2.7 x 10(-4) with a probe size approaching 4.2 nm in diameter. This method is applied to the study of the strain state in InGaAs quantum-well (QW) devices elaborated on Si substrate. Results show that the GaAs/Si mismatch does not induce in-plane strain fluctuations in the InGaAs QW region. (C) 2014 AIP Publishing LLC.

An easy-to-fabricate, low-cost, sidewall TiN/HfO 2 /Ti vertical resistive RAM (VRRAM) device is proposed. Devices with bottom electrode thickness down to 10nm were fabricated and characterized. Forming, SET and RESET voltages of respectively 2V, 0.5V and −0.5V were measured. A stable memory window of one decade was maintained after 105s at 200°C. The impact of scaling on the operating voltages and memory resistance levels was evaluated, showing a SET and RESET voltage reduction as the cell diameter is reduced. Finally the cycle-to-cycle resistance variability was addressed.

International audience; By using the most advanced devices, simulations and electrical characterizations as well as physicochemical tools, this paper revisit the role of SiGe layers in the improvement of performances of pMOS transistors. It is shown that an additional interfacial dipole effect due to Ge diffusion in the gate stack interfacial oxide needs to be added to the change of band structures in order to explain the dependence of threshold voltage on SiGe composition. The mobility gain brought by these alloys is then investigated. The relative role of Ge concentration, strain, interface states and strain relaxation is then discussed in detail.

Metal layer bonding is nowadays at the center of the latest wafer bonding researches. This technology enables innovative architectures in 3D, LED’s, MeM’s and Power devices. Unlike other metal bonding techniques, the non-thermo compression metal-metal direct bonding is performed at room temperature under atmospheric pressure ensuring minimal distortion and stress on the bonded wafers [1-3]. We have already published bonding results for copper, titanium and tungsten layers. As a summary the bonding behavior and so the bonding energy is mainly monitored by the presence of grain boundaries and the metal oxide layer at the metal surface. Smart CutTMwas also achieved with these three types of bonding [4]. We have now developed a physical chemical model approach to explain the evolution of the bonding energy and the interface structure with regards of the metal bonding integration and kinetics phenomena. We have shown that at room temperature the bonding energy is driven by the nature of the metallic oxide at the surface and the chemical reaction between the metal and the oxygen. With temperature the oxygen diffusion coefficient enhanced by the grain boundaries paths is the main key parameter, fig.1 [5]. Other integration parameters are of importance. One of them is the barrier layer (presence or nature) under the metal layer. Switching from TiN to TaN layers the bonding energy was increased by a factor of more than 2. fig.2. This was explained by the absence of void segregation during annealing at the weak TiN/ Cu interface. The same result was obtained by inserting a Ti layer between the TiN and the copper. On the other hand for copper layers of 5µm it was impossible to debond the wafers at room temperature due to the increase size of the grains. The model will be explained and detailed with extensive characterization experiments such as TEM, slice 3D SEM and picosecond analysis. Integration of metal bonding in devices and bonding energy measurement will be also discussed. Acknowledgment: The authors would like to thank the French government for its financial support under the convention OI 1262-67155, Connect 3D; SOITEC for its financial support, especially I Radu, and G Gaudin for fruitful discussions. Thanks also to Maurice Rivoire and Daniel Scevola for surface preparation and G Audoit, B Florin and Hugo Danzas for TEM sample preparation. References: [1]I. Radu, G. Gaudin, W. Van Den Daele et al “Novel Low Temperature 3D Wafer Stacking Technology for High Density Device Integration”In proceeding of: IEE ESSDERC/ 2013 [2] M. Sadaka , L. Di Cioccio et al., “Building Blocks For Wafer Level 3D Integration”, Solid State Technology, 52 (2009) p.20. [3] L. Di Cioccio, P. Gueguen, R. Taibi.et al , “An Overview of Patterned Metal /Dielectric Surface Bonding: Mechanism, Alignment and Characterization”, JECS, Volume: 158 Issue: 6 Pages: P81-P86 Published: 2011 [4] L. Di Cioccio, I. Radu, F. Baudin et al. « Wafer Level 3D Stacking using Smart CutTM and Metal-Metal Direct Bonding Technology”Proceeding of the PRIME 2012 Conference Hawai [5] M.Martinez, M.Legros,T. Signamarcheix, et al “Mechanisms of copper direct bonding observed by in-situ and quantitative transmission electron microscopy” THIN SOLID FILMS, Volume: 530,Pages: 96-99 2013