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Bats use the unusual sensory modality of echolocation to fly in complete darkness with speed and agility through complex three-dimensional environments. Their small head size and the use of high-frequency sound make interaural level differences (ILDs) their primary cue for azimuthal echolocation. In this paper, we present a neuromorphic VLSI-based system that emulates the ILD processing in the bat brainstem and midbrain. By selecting simple neural units, we propose a circuit model that is mathematically tractable and captures the essential elements of bat ILD computation. The chip includes a three-layer network of spiking neurons with 32 neurons on each layer, and the address-event representation for external interface. Emphasizing the neural spike timing and population behavior, we hope this study will contribute to the bat research community in particular as well as neuroscience in general by providing a real-time, fine-grained, neuromorphic bat echolocation simulator that will be used to address system-level performance of low-level neural algorithms. By developing functional models of the bat echolocation system, we hope to emulate the efficient implementation demonstrated by nature. Index Terms--Address-event representation (AER), auditory system, interaural level difference (ILD), neuromorphic VLSI, spiking neurons.

New formulas for interconnect capacitances have been developed based on conformal mapping. Each geometry is divided into elementary components. Capacitances of structures composed of 1-3 lines on a ground plan are expressed as a weighted sum of such elements.

We have designed, fabricated, and tested an analog very large-scale integrated (aVLSI) circuit model of a biological neuron that implements self-adaptation of its parameters. We show that the addition of this self-adaptation to our model neuron can facilitate: 1) single parameter control over a multiparameter system; 2) stability of the system to fluctuations in parameters; and 3) coordinated modulation of parameters to achieve a desired behavior. Index Terms - Adaptation, neuromorphic engineering, neuron models, nonlinear systems, subthreshold MOS design, VLSI.

A bit-serial architecture is proposed for convolving/correlating long numerical sequences by long filter algorithms. The device features a two-level interleaving framework and therefore eliminates the need for wait cycles between consecutive inputs. The fault tolerance, cascadability, feasibility in very large scale integration technology and computing performances of the architecture are evaluated. Results show that the system attains the highest possible throughput because of its two-level interleaving structure.

This paper presents a new intensity-to-time processing paradigm suitable for very large scale integration (VLSI) computational sensor implementation of global operations over sensed images. Global image quantities usually describe images with fewer data. When computed at the point of sensing, global quantities result in a low-latency performance due to the reduced data transfer requirements between an image sensor and a processor. The global quantities also help global top-down adaptation: the quantities are continuously computed on-chip, and are readily available to sensing for adaptation. As an example, we have developed a sorting image computational sensor - a VLSI chip which senses an image and sorts all pixel by their intensities. The first sorting sensor prototype is a 21 x 26 array of cells. It receives an image optically, senses it, and computes the image's cumulative histogram - a global quantity which can be quickly routed off chip via one pin. In addition, the global cumulative histogram is used internally on-chip in a top-down fashion to adapt the values in individual pixel so as to reflect the index of the incoming light, thus computing an "image of indices." The image of indices never saturates and has a uniform histogram. Index Terms - Computational sensors, image sensors, robot perception, smart sensors, vision, VLSI sensors.

A standard 2.0m CMOS process was used in implementing an object-based analog very large-scale integration (VLSI) model of selective attentional processing. The testing of segmentation- and object-based selection circuits was conducted using object-based excitatory and inhibitory feedback. Experimental results of the one-dimensional implementation of the object-based analog VLSI selective-attention system showed that the circuit's smaller nonzero output values imply the larger area of the selected object.

Substantial technological strides in the are of very large scale integration (VLSI) have enabled the possibility of building workable, cost-efficient parallel machines with tens of thousands of processors. The first known adaptive time- and VLSI-optimal sorting algorithm on a new, more powerful architecture called mesh with multiple broadcasting that is commercially available in the DAP family of multiple computers is proposed.

An on-chip differential-amplifier-based dc-to-dc voltage down converter (VDC) is proposed. The converter is a negative feedback-type voltage follower with precise internal reference voltage generator and high current drive capability. VDC converts 5 V to lower voltage so that the internal circuits of the chip are used. In this paper, 3 V is used as a test vehicle. The proposed VDC has characteristics such as output voltage remains 3 V over a large load current range (0-100 mA) and temperature dependency of 3.2 mV/[degrees] C. The VDC chip was fabricated in a 0.8-[[micro]meter] single-poly-double-metal CMOS process and layout size is 690*210 [[[micro]meter].sup.2]. The output voltage is stabilized within [+ or -]2.8% for supply voltage with [+ or -]10% variation achieved. Index Terms - DC-to-DC, low-power digital system, voltage down converter.

We consider Steiner minimal trees (SMT's) in metrics defined by given orientations. The problem is motivated by wiring considerations of VLSI chips when the wiring direction is not restricted to only horizontal and vertical. In particular, we concentrate on the case when the given orientations form angles of 0 [degrees], 60 [degrees], and 120 [degrees] ([[Lambda].sub.3]-metric) since many interesting results can be obtained which may shed light on other metrics in the family. Specifically, we show that any SMT can be transformed to one with their Steiner points located on the grid points of a multilevel grid, where the number of levels can be quite small. based on this result, we have developed a simulated annealing-based algorithm to generate near-optimal SMT's. Empirical results and comparisons with Euclidean cases are also given. Index Terms - Multilevel grid, orientation metrics, simulated annealing, Steiner tree problem, very large-scale integration.

Presented in this paper is a mathematical basis for power-reduction in VLSI systems. This basis is employed to: 1) derive lower bounds on the power dissipation in digital systems; and 2) unify existing power-reduction techniques under a common framework. The proposed basis is derived from information-theoretic arguments. In particular, a digital signal processing algorithm is viewed as a process of information transfer with an inherent information transfer rate requirement of R bits/s. Architectures implementing a given algorithm are equivalent to communication networks each with a certain capacity C (also in bits/s). The absolute lower bound on the power dissipation for any given architecture is then obtained by minimizing the signal power such that its channel capacity C is equal to the desired information transfer rate R. By including various implementation constraints, increasingly realistic lower bounds are calculated. The usefulness of the proposed theory is demonstrated via numerical calculations of lower bounds on power dissipation for simple static CMOS circuits. Furthermore, a common basis for some of the known power-reduction techniques such as parallel processing, pipelining and adiabatic logic is also provided. Index Terms - Digital CMOS, information theory, low-power.

This brief presents a synchronized feedback-type automatic gain control (AGC) architecture for SONET (synchronous optical network) OC-3 system which is suitable for scaled BJT or CMOS VLSI implementation. In this architecture, a second-order loop is utilized instead of a conventional loop, and a convenient methodology is presented for calculating the parameters of the AGC. Simulation results using micromodels in the HSPICE environment indicate that for a 20 dB dynamic range of input 77.76 MHz sinusoidal signal, the architecture yields an 80 kHz loop bandwidth and a constant 1 [V.sub.pp] output magnitude. Index Terms - Automatic gain control, SONET, VLSI architecture.

This paper describes concepts that optimize an on-chip learning algorithm for implementation of VLSI neural networks with conventional technologies. The network considered comprises an analog feedforward network with digital weights and update circuitry, although many of the concepts are also valid for analog weights. A general, semi-parallel form of perturbation learning is used to accelerate hidden-layer update while the infinity-norm error measure greatly simplifies error detection. Dynamic gain adaption, coupled with an annealed learning rate, produces consistent convergence and maximizes the effective resolution of the bounded weights. The use of logarithmic analog-to-digital conversion, during the backpropagation phase, obviates the need for digital multipliers in the update circuitry without compromising learning quality. These concepts have been validated through network simulations of continuous mapping problems.

The very large scale implementation of a treesearched vector processor array used in the block-structured image coding scheme for image compression is discussed. Each processor consists of a pipelined parallel multiplier, a bit-level accumulator, a data vector register.a partial index register and a local control unit. This tree searched processorhas been proven capable of increasing the data rate of vector quantization systems.

A low-latency and high-throughput very large scale integration tree architecture for motion estimation is presented. The architectrure implements both the three-step hierarchical search algorithm and the full-search block-matching algorithm to improve the performance of the motion estimator. It is dominated by adders that constructu the tree topology. This tree architecture also features independent data flow computation and short data path lengths, making it very suitable for supercomputing.

In this paper, we propose a generalized architecture for the 1-D discrete cosine transform (DCT), discrete sine transform (DST), and their inverses based on a general formulation. This architecture provides the flexibility to adaptively select different transform functions through a simple control signal. As compared with other unified architectures for the DCT/DST, the proposed architecture possesses better performance in the hardware cost and the number of I/O channels. The proposed design can be efficiently realized by using the distributed arithmetic approach in the VLSI implementation. Index Terms--Discrete cosine transform, discrete sine transform, distributed arithmetic, unified architecture for DCT/DST, VLSI.

A low latency architecture to compute the multiplicative inverse and division in a finite field GF([2.sup.m]) is presented. Compared to other proposals with the same complexity, this circuit has lower latency and can be used in error-correction or cryptography to increase system throughput. This architecture takes advantage of the simplicity to computing powers ([2.sup.i]) of an element in the Galois Field. The inverse of an element is computed in two stages: power calculation and multiplication. A division can be performed using only one more multiplication in the inversion circuit. Index Terms--Finite field division, finite field inverse, finite field multiplier, VLSI architecture.

A novel approach based on a modular algorithm for developing synthesizable fast Fourier transform cores is presented. The proposed method consists of parameterized commutator and processor blocks that are cascaded to implement the calculations required in important fast Fourier transform signal flow graphs. Experimental results show that the algorithm yields chip designs that are competitive with those created using manual techniques but with substantial reductions in design times.

A novel algorithm that uses a multidimensional systolic array is proposed to implement the multidimensional discrete Fourier transform. In addition, extensions of the multidimensional systolic array that is applicable for fast Fourier transform calculations are presented. The proposed algorithm combines two unique types of semisystolic arrays into a single systolic array that accepts streams of input data produced at the boundary of the array.

A variety of computational tasks in early vision can be formulated through lattice networks. The cooperative action of these networks depends on the topology of interconnections, both feedforward and recurrent ones. This paper shows that it is possible to consider a distinct general architectural solution for all recurrent computations of any given order. The Gabor-like impulse response of a second-order network is analyzed in detail, pointing out how a near-optimal filtering behavior in space and frequency domains can be achieved through excitatory/inhibitory interactions without impairing the stability of the system. These architectures can be mapped, very efficiently at transistor level, on very large scale integration (VLSI) structures operating as analog perceptual engines. The problem of hardware implementation of early vision tasks can, indeed, be tackled by combining these perceptual agents through suitable weighted sums. A 17-node analog current-mode VLSI circuit has been implemented on a CMOS 2 [[micro]meter], NWELL, single-poly, and double-metal technology, to demonstrate the feasibility of the approach. Applications of the perceptual engine to various machine vision algorithms are proposed. Index Terms - Cooperative computation, filter sensitivity, Gabor filters, resistive networks, stereo algorithms.