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Reading and writing is modelled in CSP using actions containing the symbols? and!. These reading actions and writing actions are synchronous, and there is a one-to-one relationship between occurrences of pairs of these actions. In the CPA conference 2016, we introduced the half-synchronous alphabetised parallel operator X ↓ Y, which disconnects the writing to and reading from a channel in time. We introduce in this paper an extension of X ↓ Y, where the definition of X ↓ Y is relaxed; the reading processes are divided into sets which are set-wise asynchronous, but intra-set-wise synchronous, giving full flexibility to the asynchronous writes and reads. Furthermore, we allow multiple writers to the same channel and we study the impact on a Vertex Removing Synchronised Product. The advantages we accomplish are that the extension of X ↓ Y gives more flexibility by indexing the reading actions and allowing multiple write actions to the same channel. Furthermore, the extension of X ↓ Y reduces the end-to-end processing time of the processor or coprocessor in a distributed computing system. We show the effects of these advantages in a case study describing a Controlled Emergency Stop for a processor-coprocessor combination.

Reading and writing is modelled in CSP using actions containing the symbols? and!. These reading actions and writing actions are synchronous, and there is a one-to-one relationship between occurrences of pairs of these actions. In the CPA conference 2016, we introduced the half-synchronous alphabetised parallel operator X ↓ Y, which disconnects the writing to and reading from a channel in time. We introduce in this paper an extension of X ↓ Y, where the definition of X ↓ Y is relaxed; the reading processes are divided into sets which are set-wise asynchronous, but intra-set-wise synchronous, giving full flexibility to the asynchronous writes and reads. Furthermore, we allow multiple writers to the same channel and we study the impact on a Vertex Removing Synchronised Product. The advantages we accomplish are that the extension of X ↓ Y gives more flexibility by indexing the reading actions and allowing multiple write actions to the same channel. Furthermore, the extension of X ↓ Y reduces the end-to-end processing time of the processor or coprocessor in a distributed computing system. We show the effects of these advantages in a case study describing a Controlled Emergency Stop for a processor-coprocessor combination.

Reading and writing is modelled in CSP using actions containing the symbols ? and !. These reading actions and writing actions are synchronous, and there is a one-to-one relationship between occurrences of pairs of these actions. In the CPA conference 2016, we introduced the half-synchronous alphabetised parallel operator X ⇓ Y , which disconnects the writing to and reading from a channel in time. We introduce in this paper an extension of X ⇓ Y , where the definition of X ⇓ Y is relaxed; the reading processes are divided into sets which are set-wise asynchronous, but intra-set-wise synchronous, giving full flexibility to the asynchronous writes and reads. Furthermore, we allow multiple writers to the same channel and we study the impact on a Vertex Removing Synchronised Product. The advantages we accomplish are that the extension of X ⇓ Y gives more flexibility by indexing the reading actions and allowing multiple write actions to the same channel. Furthermore, the extension of X ⇓Y reduces the end-to-end processing time of the processor or coprocessor in a distributed computing system. We show the effects of these advantages in a case study describing a Controlled Emergency Stop for a processor-coprocessor combination.

Reading and writing is modelled in CSP using actions containing the symbols ? and !. These reading and writing actions are synchronous and there is a oneto-one relationship between occurrences of pairs of these actions. It is cumbersome to ease the restriction of synchronous execution of the read and write actions. For this reason we introduce the half-asynchronous parallel operator that acts on actions containing the symbols ¿ and ¡ and study the impact on a Vertex Removing Synchronised Product.

Reading and writing is modelled in CSP using actions containing the symbols ? and !. These reading and writing actions are synchronous and there is a oneto-one relationship between occurrences of pairs of these actions. It is cumbersome to ease the restriction of synchronous execution of the read and write actions. For this reason we introduce the half-asynchronous parallel operator that acts on actions containing the symbols ¿ and ¡ and study the impact on a Vertex Removing Synchronised Product.

In certain single-core mono-processor configurations, e.g. embedded control systems, like robotic applications, comprising many short processes, process context switches may consume a considerable amount of the available processing power. For this reason it can be advantageous to combine processes, to reduce the number of context switches. Reducing the number of context switches decreases the execution time and thereby increases the performance of the application. As we consider robotic applications only, often consisting of processes with identical periods, release times and deadlines, we restrict these configurations to periodic real-time processes executing on a single-core mono-processor. These processes can be represented by finite directed acyclic labelled multi-graphs. The vertex-removing synchronised product of such graphs gives graphs that represent processes which have less context switches. To reduce the memory occupancy, the vertex-removing synchronised product removes vertices that are not reachable; i.e. represents states that can never occur. By means of a lattice, we show all possible products of a set of graphs, where the number of products is given by the Bell number. We finish with heuristics from which a set of graphs can be calculated that represents a set of processes that will not miss their deadline and which fits in the available memory.

In certain single-core mono-processor configurations, e.g. embedded control systems, like robotic applications, comprising many short processes, process context switches may consume a considerable amount of the available processing power. For this reason it can be advantageous to combine processes, to reduce the number of context switches. Reducing the number of context switches decreases the execution time and thereby increases the performance of the application. As we consider robotic applications only, often consisting of processes with identical periods, release times and deadlines, we restrict these configurations to periodic real-time processes executing on a single-core mono-processor. These processes can be represented by finite directed acyclic labelled multi-graphs. The vertex-removing synchronised product of such graphs gives graphs that represent processes which have less context switches. To reduce the memory occupancy, the vertex-removing synchronised product removes vertices that are not reachable; i.e. represents states that can never occur. By means of a lattice, we show all possible products of a set of graphs, where the number of products is given by the Bell number. We finish with heuristics from which a set of graphs can be calculated that represents a set of processes that will not miss their deadline and which fits in the available memory.