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This paper presents a study of the power dissipation repercussion on the logic and physical synthesis using LUT architectures. It is observed that the same function with different mappings on a LUT show different power dissipation. In concrete, the study reveals that the difference depends on the number of inputs of the Boolean function mapped. A power model based on this concept is developed. The power model is used to analyze the efficiency of the synthesis concerning power dissipation in LUTs. Also, a study of the fan-out and the function mapped is done. A power cost model is created to associate the fan-out and our power model. A set of circuits have been synthesized with an academic FPGA synthesis tool. The synthesis tool is used with the options of optimal delay, optimal area and delay-area trade-off. Our study shows that, in this case, synthesizing for area or delay does not affect the power dissipation. Three different LUT architectures have been studied. Results show that a four input LUT is a good choice concerning power dissipation. [ABSTRACT FROM AUTHOR]