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Soil temperature and humidity straight away influence plant growth and the availability of plant nutrients. In this work, we carried out experiments to identify the relationship between climatic parameters and plant nutrients. When the relative humidity was very high, deficiency symptoms were shown on plant leaves and fruits. But, recognizing and managing these plant nutrients manually would become difficult. However, no much research has been done in this field. The main objective of this research was to propose a machine learning model to manage nutrient deficiencies in the plant. There were two main phases in the proposed research. In the first phase, the humidity, temperature, and soil moisture in the greenhouse environment were collected using WSN and the influence of these parameters on the growth of plants was studied. During experimentation, it was investigated that the transpiration rate decreased significantly and the macronutrient contents in the plant leave decreased when the humidity was 95%. In the second phase, a machine learning model was developed to identify and classify nutrient deficiency symptoms in a tomato plant. A total of 880 images were collected from Bingo images to form a dataset. Among all these images, 80% (704 images) of the dataset were used to train the machine learning model and 20% (176 images) of the dataset were used for testing the model performance. In this study, we selected K-means Clustering for key points detection and SVM for classification and prediction of nutrient stress in the plant. SVM using linear kernel performed better with the accuracy rates of 89.77 % as compared to SVM using a polynomial kernel.

This chapter deals with introduction to system on chip (SOC), constituents of SOC and few examples of SOCs, followed by SOC development cycle, design planning, design requirements, the design center infrastructure, design and verification intellectual properties IPs, and design flows of different constituents of SOC. The chapter contains some of the VLSI processes like synthesis, DFT, and physical design which will be described in further chapters in detail. The reader should take these terms as intermediate processes in chip design till explained in detail.

This chapter describes requirement for testability, the design for testability (DFT) of SOC. It explains the methodology widely followed for SOC DFT and the automatic test pattern generation (ATPG) techniques. It covers the major challenges faced during SOC design in the context of DFT. This chapter introduces the concept of compression and need for test optimization to reduce ATE test times and its impact on economics of SOC.

This chapter deals with the SOC design as re-convergent model and physical design process of the system on chip (SOC). The complete physical design flow is explained in this chapter starting from floor plan to design tape-out. It defines the re-convergent model of the SOC design and introduces various design file formats which are written out in the physical design. The chapter also deals with the photolithography and pattern transfer from the design tape-out.

This chapter deals with the importance of SOC design verification, plan and strategies adopted for verification. It defines functional simulation, functional coverage, code coverage, and other important terms used in verification. Importance of FPGA validation and how it complements the SOC design verification is explained in this chapter. Most of the simulation concept of SOC design verification explained in the chapter can be seen in the verification of the reference designs provided in Chapter 12.

This chapter discusses different VLSI design techniques highlighting coding style for synthesis. It covers important design concepts like synchronous and asynchronous circuits, clock and reset circuits, clock domain crossovers, speed matching, and so on. In addition, it deals with behavioral modelling, structural modelling, standard cell libraries, and different file formats generated during design phases with SOC design context. The reader is advised to refer VLSI logic design books (A Verilog HDL primer, J Bhaskar; VHDL primer Jayaram Bhaskar, A System Verilog primer, J Bhaskar) for fundamental understanding of VLSI design and books on hardware description languages like Verilog and VHDL for clear understanding and mastering them.

This chapter deals with the designing of an IoT system for environment monitoring. It demonstrates in detail how the requirements are converted to an actual product. Reader can use the content of this chapter as a reference to design any IoT solution of their choice. This chapter also has an approach note to implement the design as a system on chip (SoC) for further miniaturization.

This chapter describes Industry revolution along with its history of industry revolutions, Industry 4.0 with Internet of Things (IoT), Industrial Internet of Things (IIoT), and M2M communication technologies as enabling technologies. As it sets the platform for design fundamentals of IoT, various terms associated with the Internet of Things are defined.

This chapter details application development technologies in IoT systems. The application technologies and protocols used to develop applications which run on devices, gateways, and cloud interfaces with the user or surrounding environment. This chapter explains different protocols and their use in application development.

This chapter defines various communication protocols for constrained devices and constrained lossy and low-power networks.

Earlier chapters concentrated capturing and aggregating data and managing networks. This chapter deals with database formation, organization, and management of such collected from a large number of sensor devices and analyzing them.

Plants need nutrients to develop normally. The essential nutrients like carbon, oxygen, and hydrogen are obtained from sunlight, air, and water to prepare food and plant growth. For healthy growth, plants also need macronutrients such as Potassium, Calcium, Nitrogen, Sulphur, Magnesium, and Phosphorus in relatively great quantities. When a plant doesn’t find necessary nutrients for its growth inadequate amount, deficiency of plant nutrients occur. Plants exhibit various symptoms to indicate the deficiency. Automatic identification and differentiation of these deficiencies are very important in the greenhouse environment. Deep Neural Networks are extremely efficient in image categorization problems. In this work, we used the part of the pre-trained deep learning model i.e. Transfer Learning model to detect the nutrient stress in the plant. We compared three different architectures including Inception-V3, ResNet50, and VGG16 with two classifiers: RF and SVM to improve, classification accuracy. A total of 880 images of Calcium and Magnesium deficiencies in the Tomato plant from the greenhouse were collected to form a dataset. For training, 704(80%) images are used and for testing, 176(20%) images are used to examine the model performance. Experimental results demonstrated that the largest accuracy of 99.14% has resulted for the VGG16 model with SVM classifier and 98.71% for Inception-V3 with Random Forest Classifier. For a batch size of 8 and epochs equal to 10, the Inception -V3 architecture attained the highest validation accuracy of 99.99% and the least validation loss of 0.0000384 on an average.

This chapter discusses standard protocols related to M2M communication, with reference to ISO’s OSI layer architecture and its modifications required to connect lightweight device architectures to conventional systems on the Internet. This chapter also deals with necessary modifications in Ethernet stack to accommodate IoT device connectivity to networked device. It introduces different application protocols like HTTP, MQTT, and CoAP.

This chapter deals with the architecture, design, and development of software for IoT systems. IoT software is very complex as it involves device software, application software, and communication software and should comply with different standards. The chapter highlights the importance of guidelines for good firmware IoT architecture.

This chapter explains the different methods of M2M communication and M2M technologies, history of M2M communication, applicable standards and protocols, architectural frameworks of M2M communication, and examples from different application domains.

This chapter has three parts: Part 1 has a set of questions from each chapter for the reader to test their understanding. Part 2 has firmware programs (code clips) for the most used interfaces on Arduino board. The design examples presented in Part 2 can be tried on development boards or IDEs on your systems. It is necessary to download the correct files from the open-source sites depending on the operating system of the system used. Part 3 deals with the design approach note to the development of IoMT- and IoS-based healthcare ecosystem solution.

This chapter deals with the layered architecture and describes design flow of IoT device for an application in a step-by-step manner. Also discussed in this chapter are the different types of architectures including edge computing- and cloud computing-based IoT solutions. IoT design is explained with the help of body temperature monitoring IoT as an example design.

This chapter deals with the design for manufacturability (DFM) and other requirements to be considered for IoT product development and business models enabled by IoT and IIoT solutions. The chapter also introduces concept of business model innovation and its importance for sustained success.

Wireless Sensor Network has been increasingly used for remote monitoring system and its adoption in increasing exponentially for larger application too. However, there are various challenges associated with both resource management and security that roots up when the deployment scale goes massive and distributed in order. The proposed system considers a case study of smart city management where the problems associated with data transmission and security has been addressed. This is carried out using the provisioning of urban environment monitoring system that is an essential system for smart city projects to assure the citizens' better-quality well-being. The scalable and effective urban environment monitoring system requires a seamless transmission of the data from the sensor nodes to the analytics engine. The existing architectures are more designed to suit very specifically the use-cases. As a contribution, the proposed system introduces a cost-effective architecture for environmental monitoring in urban zones of smart city named as a Smart Sensor Surveillance System (4S-UEM). The core idea of the proposed system is to offer a balance between resource efficiency and resilience secure communication in large scale deployment of WSN considering smart city as deployment and assessment area. The proposed system makes use of urban geographical clustering process in order to develop an organized structure of sensor nodes. Different from any existing studies, the proposed system introduces data analytical engine followed by secure routing using gateway. The design of the proposed system is carried out using layered architecture of the communication model targeting towards a cost-effective, energy optimal, and secure data transmission to the analytics engine.

Processing of the multiple data streams demand highperformance multiple transfers overburden the Processor System on Chips (SoC) in real time multimedia processing applications. High performance direct memory access (DMA) controller eases the processor as it performs bulk data transfer without the intervention of processor. This is true even in most artificial intelligence (AI) based systems and interleaving functions in communication systems where high-speed bulk data transfers are required. This is achieved by the design of Enhanced Direct Memory Access (EDMA) Controller, for high speed bulk data transfers. Paper presents the design of enhanced DMA core which is synthesizable ready to integrate for high performance AI based Digital Signal Processing SoC. The EDMA core is used for flexible Memory Access and bulk data transfers. EDMA core support several methods for data transfer between an input or output (I/O) device and the core processing unit. The processor in the SoC is used to program the Direct Memory Access (DMA) transfer instructions and actual transfers are performed by the EDMA core without the interference of processor. The EDMA design supports flexible addressing modes like linear, circular, step for bulk data transfers. The EDMA core is planned to be verified with test cases as in realistic application scenarios of interleaving, real time video processing.

Due to vast integration density in CMOS technology, faults in the embedded or external memory have been increased. This manifests as single-cell upsets (SCU) and multiple cell upsets (MCU) for function, especially in flash memories. Flash memory provides far greater storage capacity at lower operating cost than SDRAM. Memories that operate in harsh environment like space can suffer from multiple errors. Due to the faults, data can be flipped from 1 to 0 or 0 to 1 or sometimes the message bits even get deleted. So, an embedded error correction code-based functional block is used along with dense memory, to ensure that the errors do not cause data corruption. This paper presents a method to protect memories from multiple cell upsets by adding redundancy. The error detection and correction can be done by using flexible unequal error control code (FUEC)-based design. The FUEC can detect and correct double, triple, and quadruple adjacent error. By using this method, low redundancy can be achieved in memory. The ECC engine was designed successfully, verified, and ready for integration to the memory. The design details are discussed below.

This paper discusses the modeling of a multi-mode digitally controlled switching mode buck converter to power a system-on-chip (SOC). It operates in digital pulse width modulation mode under heavy and medium load conditions, whereas in digital pulse frequency modulation mode it operates under light load conditions to obtain high-power conversion efficiency over a wide range of load current. In PWM mode of operation, Σ−∆ modulator-based digital pulse width modulator (DPWM) is implemented which provides high-resolution, low-power architecture to supply accurate, precise and low ripple content voltage to SOCs. A type III compensator is designed to improve the dynamic performance of the buck converter. Maximum efficiency of 88.48% is obtained at 0.2 A under PWM mode of operation. An output voltage accuracy of 0.25% is achieved against a target value of 1%. The load current and line voltage transient responses are verified by considering the different range of load current and line voltage variations. As an example, for a load variation from 150 to 400 mA, the undershoot is 30 mV, and when the load varies from 400 to 150 mA, the overshoot is 32 mV. The % peak overshoot/undershoot is around 3%. The response time of the power supply when load variations occur (150–400 mA and vice versa) is 3 μs. The steady-state output voltage is 1.002 V, when the input battery voltage varied from 2.5 to 3.2 V and vice versa; in addition, the undershoot and overshoot in output voltage are 20 and 25 mV, respectively. The time taken by the power supply to settle to a steady value of 1.0025 is 10 μs. Light load or power save mode efficiency is improved by using a DPFM mode of operation. The minimum efficiency obtained is 66.62% at 0.001 A. The % efficiency lies between 66.62 and 85% for a load current range of 0.001–0.1 A

This chapter deals with the physical design verification of a system on chip, which are logic equivalence check and STA analysis flow carried out at every stage of the physical design of a SOC. The chapter explains electrical rules checks (ERC), verification of interconnect effects, like cross talk, IR analysis, and the antenna effects. It also deals with design rule checks (DRC) and design for manufacturing (DRM) rules check for the SOC design before the design tape-out to the fabrication house.

This chapter explain the timing analysis techniques, tools for timing analysis, concept of design corners, challenges of on-chip variations in advanced technology nodes, and a few tips to address those challenges for achieving SOC timing closure.