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The magnitude of a seismic event can be estimated by measuring seismic energy, seismic moment, and relationship between the energy and seismic magnitude (M)，etc. However, it is impossible to traditionally locate a microseismic event, including determining its magnitude, because its records are submerged in the background noise in most of cases. Comparing the microseismic magnitudes at different regions and with different causes, studying their mechanisms，we first extend the definition of the Richter magnitude to the microseismic range. Then, based on the scanning output of the minimum ratio of signal-to-noise in the available vector processing for microseismic monitoring, we estimate their equivalent Richter magnitude. The microseismic magnitudes induced by different causes are compared.

Road network extraction plays a critical role in data updating, urban development, and decision support. To improve the efficiency of labeling road datasets and addressing the problems of traditional methods of manually extracting road networks from high-resolution images, such as their slow speed and heavy workload, this paper proposes a semi-automatic method of road network extraction from high-resolution remote-sensing images. The proposed method needs only a few points to extract a single road in the image. After the roads are extracted one by one, the road network is generated according to the width of each road and the spatial relationships among the roads. For this purpose, we use regional growth, morphology, vector tracking, vector simplification, endpoint modification, road connections, and intersection connections to generate road networks. Experiments on four images with different terrains and different resolutions show that this method has high extraction accuracy under different image conditions. The comparisons with the semi-automatic GVF-snake method based on regional growth also showed its advantages and potentiality. The proposed method is a novel form of semi-automatic road network extraction, and it significantly increases the efficiency of road network extraction. [ABSTRACT FROM AUTHOR]

A target velocity sampling method named the Relative Speed Tabulation (RST) is proposed for the efficient treatment of resonance elastic scattering in the Monte Carlo simulation utilizing graphics processing units (GPU). The RST method samples the relative speed between a neutron and a target nucleus by employing pretabulated probabilities of relative speeds. The target velocity is then determined from the sampled relative velocity and the neutron speed. The motivation was to avoid the rejection process of the Doppler Broadening Rejection Correction (DBRC) method, which can incur a significant reduction in the parallel performance of vector processors, such as GPUs, due to its largely varying rejection rates. The RST can also overcome the weakness of large variance of the Weight Correction Method (WCM), which would involve drastic changes in neutron weights. The verification results obtained for the Mosteller benchmark problems demonstrate that the RST is equivalent to the DBRC in accuracy, while the calculation speed remains at the same level of the WCM. [ABSTRACT FROM AUTHOR]

Developing efficient graph algorithms implementations is an extremely important problem of modern computer science, since graphs are frequently used in various real-world applications. Graph algorithms typically belong to the data-intensive class, and thus using architectures with high-bandwidth memory potentially allows to solve many graph problems significantly faster compared to modern multicore CPUs. Among other supercomputer architectures, vector systems, such as the SX family of NEC vector supercomputers, are equipped with high-bandwidth memory. However, the highly irregular structure of many real-world graphs makes it extremely challenging to implement graph algorithms on vector systems, since these implementations are usually bulky and complicated, and a deep understanding of vector architectures hardware features is required. This paper presents the world first attempt to develop an efficient and simultaneously simple graph processing framework for modern vector systems. Our vector graph library (VGL) framework targets NEC SX-Aurora TSUBASA as a primary vector architecture and provides relatively simple computational and data abstractions. These abstractions incorporate many vector-oriented optimization strategies into a high-level programming model, allowing quick implementation of new graph algorithms with a small amount of code and minimal knowledge about features of vector systems. In this paper, we evaluate the VGL performance on four widely used graph processing problems: breadth-first search, single source shortest paths, connected components, and page rank. The provided comparative performance analysis demonstrates that the VGL-based implementations achieve significant acceleration over the existing high-performance frameworks and libraries: up to 14 times speedup over multicore CPUs (Ligra, Galois, GAPBS) and up to 3 times speedup compared to NVIDIA GPU (Gunrock, NVGRAPH) implementations. [ABSTRACT FROM AUTHOR]

Road network extraction plays a critical role in data updating, urban development, and decision support. To improve the efficiency of labeling road datasets and addressing the problems of traditional methods of manually extracting road networks from high-resolution images, such as their slow speed and heavy workload, this paper proposes a semi-automatic method of road network extraction from high-resolution remote-sensing images. The proposed method needs only a few points to extract a single road in the image. After the roads are extracted one by one, the road network is generated according to the width of each road and the spatial relationships among the roads. For this purpose, we use regional growth, morphology, vector tracking, vector simplification, endpoint modification, road connections, and intersection connections to generate road networks. Experiments on four images with different terrains and different resolutions show that this method has high extraction accuracy under different image conditions. The comparisons with the semi-automatic GVF-snake method based on regional growth also showed its advantages and potentiality. The proposed method is a novel form of semi-automatic road network extraction, and it significantly increases the efficiency of road network extraction.

This paper introduces a new datatype, the High-Precision Anchored (HPA) number, that allows reproducible accumulation of floating-point (FP) numbers in a programmer-selectable range. The new datatype has a larger significand and a smaller range than existing FP formats and has much better arithmetic and computational properties. In particular, it is associative, parallelizable, reproducible and correct. The paper also describes how HPA processing can be implemented as part of Arm's new Scalable Vector Extension (SVE) together with proposals for new instructions aimed specifically at the new datatype. For the modest ranges that will accommodate most problems, HPA processing is much faster than FP arithmetic: performance modelling shows 2-lane HPA accumulation of FP64 operands is 9.5 times faster on Arm's new vector architecture than double double accumulation and accelerates a recently published software algorithm for 3-lane reproducible FP summation by a factor of 5.6. This paper also discusses instruction-level optimizations for FP32 and FP16 summations that further increase HPA performance relative to FP64 accumulations. [ABSTRACT FROM AUTHOR]

Techniques for the experimental determination of velocity fields such as particle image velocimetry (PIV) can often be hampered by spurious vectors or sparse regions of measurement which may occur due to a number of reasons. Commonly used methods for detecting and replacing erroneous values are often based on statistical measures of the surrounding vectors and may be influenced by further poor data quality in the region. A new method is presented in this paper using Linear Stochastic Estimation for vector replacement (LSEVR) which allows for increased flexibility in situations with regions of spurious vectors. LSEVR is applied to PIV dataset to demonstrate and assess its performance relative to commonly used bilinear and bicubic interpolation methods. For replacement of a single vector, all methods performed well, with LSEVR having an average error of 11% in comparison to 14% and 18% for bilinear and bicubic interpolation respectively. A more significant difference was found in replacement of clusters of vectors which showed average vector angle errors of 10°, 9° and 6° for bilinear, bicubic and LSEVR respectively. Error in magnitude was 3% for both interpolation techniques and 1% for LSEVR showing a clear benefit to using LSEVR for conditions that require multiple clustered vectors to be replaced.

Recent activity in near-data processing has built or proposed systems that can exploit technologies such as 3D stacks, in-situ computing, or dataflow devices. However, little effort has been applied to exploit the natural parallelism and throughput of DRAM. This article details research from Micron Technology in the area of processing in memory as a form of memory-centric computing. In-Memory Intelligence (IMI) attempts to place a massive array of bit-serial computing elements on pitch with the memory array, as close to the information as possible. This contrasts with near-memory devices that rely on some form of storage but must communicate with that storage via a fast, low-latency interface. Initial simulations and models show stair-step improvements in performance and power for various applications. Such technology allows DRAM to provide functionality in a heterogeneous system to alleviate the pressures of the von-Neumann barrier. [ABSTRACT FROM PUBLISHER]

Sorted lists of integers are commonly used in inverted indexes and database systems. They are often compressed in memory. We can use the single-instruction, multiple data (SIMD) instructions available in common processors to boost the speed of integer compression schemes. Our S4-BP128-D4 scheme uses as little as 0.7 CPU cycles per decoded 32-bit integer while still providing state-of-the-art compression. However, if the subsequent processing of the integers is slow, the effort spent on optimizing decompression speed can be wasted. To show that it does not have to be so, we (1) vectorize and optimize the intersection of posting lists; (2) introduce the SIMD GALLOPING algorithm. We exploit the fact that one SIMD instruction can compare four pairs of 32-bit integers at once. We experiment with two Text REtrieval Conference (TREC) text collections, GOV2 and ClueWeb09 (category B), using logs from the TREC million-query track. We show that using only the SIMD instructions ubiquitous in all modern CPUs, our techniques for conjunctive queries can double the speed of a state-of-the-art approach. Copyright © 2015 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

This paper proposes a new processor architecture called VVSHP for accelerating data-parallel applications, which are growing in importance and demanding increased performance from hardware. VVSHP merges VLIW and vector processing techniques for a simple, high-performance processor architecture. One key point of VVSHP is the execution of multiple scalar instructions within VLIW and vector instructions on unified parallel execution datapaths. Another key point is to reduce the complexity of VVSHP by designing a two-part register file: (1) shared scalar–vector part with eight-read/four-write ports 64×32-bit registers (64 scalar or 16×4 vector registers) for storing scalar/vector data and (2) vector part with two-read/one-write ports 48 vector-registers, each stores 4×32-bit vector data. Moreover, processing vector data with lengths varying from 1 to 256 represents a key point for reducing the loop overheads. VVSHP can issue up to four scalar/vector operations in each cycle for parallel processing a set of operands and producing up to four results to be written back into VVSHP register file. However, it cannot issue more than one memory operation at a time, which loads/stores 128-bit scalar/vector data from/to data memory. The design of our proposed VVSHP processor is implemented using VHDL targeting the Xilinx FPGA Virtex-5 and its performance is evaluated. [ABSTRACT FROM AUTHOR]

This paper describes the main ideas of a GNSS SDR receiver and its implementation. Aims of the development, advantages, and some specific details are discussed. Particular attention is paid to the issue of security in GNSS receivers used for special purposes and some strategies of tracking. The idea of a snapshot receiver is briefly mentioned. [ABSTRACT FROM AUTHOR]

SUMMARY In many important applications-such as search engines and relational database systems-data are stored in the form of arrays of integers. Encoding and, most importantly, decoding of these arrays consumes considerable CPU time. Therefore, substantial effort has been made to reduce costs associated with compression and decompression. In particular, researchers have exploited the superscalar nature of modern processors and single-instruction, multiple-data (SIMD) instructions. Nevertheless, we introduce a novel vectorized scheme called SIMD-BP128⋆ that improves over previously proposed vectorized approaches. It is nearly twice as fast as the previously fastest schemes on desktop processors (varint-G8IU and PFOR). At the same time, SIMD-BP128⋆ saves up to 2 bits/int. For even better compression, we propose another new vectorized scheme (SIMD-FastPFOR) that has a compression ratio within 10% of a state-of-the-art scheme (Simple-8b) while being two times faster during decoding. Copyright © 2013 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]