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1. A Linear Complexity Algorithm for the Generation of Multiple Input Single Output Instructions of Variable Size

2. High-Bandwidth Address Generation Unit

3. Trends in Low Power Handset Software Defined Radio

6. PISC: Polymorphic Instruction Set Computers

7. Rescheduling for Optimized SHA-1 Calculation

8. SAD Prefetching for MPEG4 Using Flux Caches

9. Sandbridge Software Tools

10. Flux Caches: What Are They and Are They Useful?

11. Reconfigurable Multiple Operation Array

12. Interprocedural Optimization for Dynamic Hardware Configurations

13. A Low-Power Multithreaded Processor for Baseband Communication Systems

14. Memory Bandwidth Requirements of Tile-Based Rendering

15. Dynamic Hardware Reconfigurations: Performance Impact for MPEG2

16. The Virtex II ProTM MOLEN Processor

17. High-Level Energy Estimation for ARM-Based SOCs

18. Loading ρμ-Code: Design Considerations

19. The Molen Programming Paradigm

20. A Java-Enabled DSP

21. A 2D Addressing Mode for Multimedia Applications

24. A Dynamic Pricing and Bidding Strategy for Autonomous Agents in Grids

25. Vectorized AES Core for High-throughput Secure Environments

26. BRAM-LUT Tradeoff on a Polymorphic DES Design

27. Synthesis of Regular Expressions Targeting FPGAs: Current Status and Open Issues

28. A Linear Complexity Algorithm for the Automatic Generation of Convex Multiple Input Multiple Output Instructions

29. Systematic Customization of On-Chip Crossbar Interconnects

30. Partially Reconfigurable Point-to-Point Interconnects in Virtex-II Pro FPGAs

32. Improving SHA-2 Hardware Implementations

33. The PowerPC Backend Molen Compiler

34. SCISM vs IA-64 Tagging: Differences/Code Density Effects

35. Visual Data Rectangular Memory

43. Local Distributed Agent Matchmaking

44. The MOLEN ρμ-Coded Processor

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