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Low latency beamforming using phased antenna arrays is the key for practical deployment of envisioned millimetre wave (mmWave) Gbps mobile networks. This work aims towards reducing the overhead of the exhaustive sector‐level sweep phase of the analog beamforming adopted in the IEEE 802.11ad standard. This work is the first to propose the use of reconfigurable antenna single RF chain in the sub‐6 GHz new radio (NR) band to aid codebook‐based beam selection in the mmWave band of the NR. We exploit the congruence between the spatial propagation signatures of signals at both mmWave and sub‐6 GHz frequencies to reduce the beam search space. The simulation results show a significant reduction in mmWave beam search overhead up to 70% on average and 80% with an average gain loss of 3dB.

This paper presents the integration of resonant clocking to multi-die architectures to synchronize individual chiplets connected through an active silicon interposer. The proposed inter-chiplet synchronization through the active silicon interposer rotary oscillator array (ASI-ROA) provides a unitary clock domain to the multiple die (i.e. multiple chiplets) in the package with a very low design overhead. System performance analysis is performed with parasitics-extracted, post-layout simulation models of two different sizes of representative heterogeneous multi-die architectures, each with varying number of RISC-V cores per die. Each RISC-V core of the multi-die package belongs to the unitary clock domain, designed with ASI-ROA to operate at a frequency of 2 GHz. The proposed architecture is investigated for robustness in frequency and skew across the multi-die system (MDS) with SPICE based simulations of post layout models, demonstrating variations of only 80 MHz for a 2 GHz target frequency. The power savings are upto 41% for the overall MDS, compared to an equivalent implementation with a contemporary ADPLL used to synchronize the multiple chiplets over the active interposer. The average clock skew of the completely resonant architecture presented in this work is 8.2 ps.

Envisioned analog beamforming, high-gain, phased antenna array systems operating at millimeter-wave (mmWave) frequencies require a fast beam selection process for practical implementation in mobile units in a changing propagation environment. This paper proposes a novel direction of arrival (DoA) estimation technique using a single RF chain reconfigurable Alford loop antenna at sub-6GHz frequencies to facilitate a rapid optimal beam selection process at mmWave frequencies. Measurement-based DoA estimation, demonstration of reduced beam scanning overhead at mmWave frequencies, and design of a software-defined-radio (SDR)-based testbed for evaluating the proposed integrated system are addressed.

On-chip wireless interconnects provide signal broadcasting and link shortcuts for improved latency and throughput, useful considering the increase of the number of processing elements on a chip. In this work, a through-silicon via antenna (TSV_A) for on-chip wireless communication is proposed. TSV_A significantly improves the wireless interconnect performance over current solutions of on-chip antennas, which occupy a large area of the chip and are not capable of far-reaching transmission. Printed circuit board (PCB) prototypes are designed and fabricated to validate the proposed TSV_A. The PCB prototype of the TSV_A has an insertion loss of 5-10 dB at a distance of similar or equal to 20 mm, measured in PCB and validated with high fidelity 3D finite element method simulation results. TSV_A has improved path loss, smaller size, and lower manufacturing costs due to the well-established TSV fabrication process for 3D-ICs. Projections for an on-chip 3D-IC operation indicate up to 40 dB improved signal strength compared to other on-chip antennas, with an insertion loss of similar or equal to 3-5 dB up to a 30 mm distance.

A physical design methodology is presented to synchronize digital application specific integrated circuit (ASIC) designs by a resonant rotary clock network. One novelty of the proposed RotaSYN flow is that the ASIC products of RotaSYN can operate at previously unattainable (relatively) low-frequency ranges of hundreds of megahertz. The dynamic resonant frequency divider is used to implement the low-frequency operation; and low in comparison to the norm of gigahertz-range of operation for resonant clocking reported in this paper. In SPICE -based simulations, the efficacy of the proposed flow and novel algorithms in RotaSYN is demonstrated using performance metrics of the wirelength, skew, and power on international symposium on physical design-10 clock benchmark circuits. In addition, RotaSYN is compared to three publicly available industrial designs that include the ARM Cortex M0 against equivalent clocks generated with a traditional phase locked loop (PLL) and distributed with an industrial clock tree synthesis tool flow. The RotaSYN methodology is implemented at three different target frequencies of 880 MHz, 500 MHz, and 220 MHz for the industrial designs. SPICE simulations show an average of 29% power savings for the industrial designs overall, solely thanks to 66% power savings on the clock generation and distribution networks, operating at a frequency of 880 MHz on comparison to the PLL-based design with a clock tree synthesized with an industrial EDA tool.

The discovery of the applicability of radio-frequency identification (RFID) for inductive coupling to a stretchable fabric antenna has enabled biomedical sensing applications using wearable, passive, unobtrusive smart garment devices. Stretching of knitted fabric antennas embedded into wearable garments allows correlation of physical properties of backscattered RFID interrogation signals to human biomedical activities such as respiration, uterine contractions, limb movements, and heartbeats. We have knit comfortable, powerless, passive antennas on smart garment devices to provide potential improvements in the hospital and home setting for uterine monitoring during pregnancy, apnea detection in infants, and other applications. However, these RFID properties must be (a) measured in real time, (b) denoised and processed in real time, and (c) compared against state-of-the-art medical devices currently in use, with unsupervised or semi-unsupervised learning techniques. We address the challenges faced in designing and fabricating knitted wearable unobtrusive smart garment devices, as well as in designing network-enabled RFID software processing framework for real-time collection, filtering, and classification of biomedical sensed data.

In this paper, the first comprehensive methodology is presented for design of low power adiabatic circuits inclusive of the adiabatic core design and the power-clock generation. Prior works have focused on either designing adiabatic cores or the power clock generation circuit, only. These non-comprehensive views can misrepresent the performance savings and fail to address the opportunities at integration. In this work, a comprehensive solution is presented that also features a unique innovation for the power clock generation circuit in step-charged circuits designed with rotary traveling wave oscillators (RTWO) and adiabatic frequency dividers. In experimentation, SPICE based simulations are performed at 416 MHz and 330 MHz in the 90 nm technology node and compared to CMOS based implementations, as well as other known power-clock generation techniques. A 32-bit CMOS adder consumes 3.5× more power when compared to the proposed 32-bit ECRL adder operating at a frequency of 416 MHz. Furthermore, 1000 32-bit CMOS adders in parallel consumes 3.4× more power when compared to 1000 32-bit ECRL adders in parallel designed with the proposed architecture at a frequency of 416 MHz.

On-chip wireless links offer improved network performance due to long distance communication, additional bandwidth, and broadcasting capabilities of antennas. This work challenges the on-chip antenna design conventions, and pushes toward a Through-Silicon Via-based antenna design called TSV_A that establishes multi-band wireless communication through the silicon substrate medium with only a 3 dB loss over a 30mm on-chip distance. The TSV_A performance is evaluated in both Finite Element Method and system-level Network-on-Chip (NoC) simulations. A comparison to traditional wire-based NoCs, analysis of wireless multi-bands, and technology scaling to demonstrate the substantial area improvements compared to traditional wireless NoCs (up to 99.88%) are performed. Simulation results show an improvement in network latency up to similar to 13% (average improvement of similar to 7%), energy-delay improvements of similar to 34% on average, and an improvement in throughput up to similar to 34% (average improvement of similar to 23%), using Wireless NoC with multi-band TSV_As. The improved signal performance of TSV_A, and multi-band capabilities, are ideal for wireless intercell communication for programmable metasurfaces with dedicated communication layers.

Advances in interconnect technologies for system-in-package manufacturing have re-introduced multi-chip module (MCM) architectures as an alternative to the current monolithic approach. MCMs or multi-die systems implement multiple smaller chiplets in a single package. These MCMs are connected through various package interconnect technologies, such as current industry solutions in AMD's Infinity Fabric, Intel's Foveros active interposer, and Marvell's Mochi Interconnect. Although MCMs improve manufacturing yields and are cost-effective, additional challenges on the Network-on-Chip (NoC) within a single chiplet and across multiple chiplets need to be addressed. These challenges include routing, scalability performance, and resource allocation. This work introduces a scalable MCM 3D interconnect infrastructure called "MCM-3D-NoC" with multiple 3D chiplets connected through an active interposer. System-level simulations of MCM-3D-NoC are performed to validate the proposed architecture and provide performance evaluation of network latency, throughput, and EDP.

The emergence of Network-on-Chip (NoCs) as a scalable interconnection infrastructure for Chip Multi-Processors (CMPs) creates the need to analyze the degradation and lifetime repercussions incurred by network traffic from exa-scale and distributed workloads. Reliability methods and redundancies are in place to circumvent defective parts or to roll back to a previous safe state. These reliability techniques are reactive in nature and do not focus effort in avoiding degradation which may result in full system failure. Current methods for improving degradation and lifetime focus on design and runtime optimizations. This paper proposes a workload-aware routing algorithm, which complements known techniques and optimizes the overall network traffic balance. The end product is a methodology that utilizes workload signatures and priority-based routing to improve port and router utilization across the network. The proposed WAR algorithm stays within ≈2% of the latency and average hop count of a NoC using XY routing. Simulation results show an improvement in network traffic balance upto ≈17% (average improvement of ≈8.6%) with WAR on NoCs for lifetime improvement.

The emergence of Network-on-Chip (NoC) as a communication paradigm for Multi-Processor System-on-Chips (MPSoCs) significantly exacerbates the need to provide a methodology that optimizes the energy consumption of the overall system. This is especially important when factoring in current Network-on-Chip advances which have multiple communication media such as on-chip wireless or nano-photonics links, hybrid with traditional wired links. All of these media have different energy profiles, and if not taken into consideration the system will incur a higher power consumption throughout the runtime of the application. In this work, the case for EDP (energy-delay product) optimization between different levels of a multi-level Network-on-Chip is presented. Using a dynamic, energy aware algorithm, the EDP improvement is compared to a multi-level Network-on-Chip using a statically optimized routing. The proposed routing algorithm handles the different types of energy-delay profiles of multiple links. The end product is a methodology that lowers the overall energy consumption by optimizing the energy profile of the Network-on-Chip while also minimizing the network delay.

Network-on-Chip (NoC) is a communication paradigm capable of facilitating a scalable interconnection infrastructure for multi core processors. Wireless NoCs have been introduced to improve the communication performance over long-distance processing nodes. Current on-chip antennas used in wireless NoCs communicate predominantly through surface waves, where the efficacy of the wireless nodes is partially determined by the radiation efficiency and transmission gain limited due to the conductivity loss of the silicon substrate. Recently, an on-chip propagation technique of radio waves was introduced, through the un-doped silicon layer as opposed to surface-waves prevalent in literature. The through-substrate propagation waves provide a unique solution to overcome the challenge of long-distance communication between processing nodes. In this work, overall improvements are shown compared to traditional wireless NoCs with the placement of antennas on undoped silicon (i.e. communicating through surface waves), simulated in NoC architectures across performance metrics of area, power consumption and latency.

SoC (System on chip) technology has rapidly developed in recent years, stimulating emerging research areas such as investigating the efficacy of wireless network interconnection within a single chip or between multiple chips. However the design of the on-chip antenna faces the challenge of obtaining high radiation efficiency and transmission gain due to conductive loss of the silicon substrate. A new on-chip propagation mechanism of radio waves, which takes advantage of the un-doped silicon layer, is developed in order to overcome this challenge. It was found that by properly designing the dimension of silicon wafer, the un-doped silicon layer is able to act like a waveguide. Most of the energy is directed to the approximately lossless the undoped silicon layer of high resistivity instead of attenuating in the doped silicon substrate or radiating to the air. HFSS modeling and simulation results are provided to show that efficiency, gain and directivity of the on-chip antenna are greatly improved. In addition, this type of antennas can be easily reconfigured, which as a result, makes wireless SoCs with wireless interconnects or even a wireless network on PCB (Printed Circuit Board) possible.