Search

We report the first demonstration of InAs FinFETs with fin width \textrm W{\mathrm{fin}} in the range 25–35 nm, formed by inductively coupled plasma etching. The channel comprises defect-free, lattice-matched InAs with fin height \textrm H{\mathrm{fin}}=20 nm controlled by the use of an etch stop layer incorporated into the device heterostructure. For a gate length \textrm L{{\textrm {g}}}=1~\mu \text{m} , peak transconductance \textrm g{{\textrm {m,{\mathrm{ peak}}}}}=1430~\mu \text{S}/\mu \text{m} is measured at \textrm V{\textrm {d}}=0.5 V demonstrating that electron transport in InAs fins can match planar devices. [ABSTRACT FROM PUBLISHER]

Vertical n-channel tunnel field-effect transistors (TFETs) with tunneling normal to the gate based on an n+ In∞=0.53->;1GaAs/p+ InP heterojunction have been demonstrated to exhibit simultaneously a high ION/IOFF ratio of 6 × 105, a minimum subthreshold swing (SS) of 93 mV/dec, and an on-current of 20 μA/μm at VDS = 0.5 V and a gate swing of 1.75 V at 300 K, a record TFET performance. The significant improvement in device performance is ascribed to the adoption of a thin equivalent oxide thickness (EOT) of ~1.3 nm for improved electrostatics and the use of plasma-enhanced chemical vapor deposition SiN∞ mesa passivation to preserve the integrity of the thin exposed semiconductor layers. [ABSTRACT FROM AUTHOR]

The integration of III-V semiconductors on silicon (Si) substrate has been an active field of research for more than 30 years. Various approaches have been investigated, including growth of buffer layers to accommodate the lattice mismatch between the Si substrate and the III-V layer, Si- or Ge-on-insulator, epitaxial transfer methods, epitaxial lateral overgrowth, aspect-ratio-trapping techniques, and interfacial misfit array formation. However, manufacturing standards have not been met and significant levels of remaining defectivity, high cost, and complex integration schemes have hampered large scale commercial impact. Here we report on low cost, relaxed, atomically smooth, and surface undulation free lattice mismatched III-V epitaxial films grown in wide-fields of micrometer size on 300 mm Si(100) and (111) substrates. The crystallographic quality of the epitaxial film beyond a few atomic layers from the Si substrate is accomplished by formation of an interfacial misfit array. This development may enable future platforms of integrated low-power logic, power amplifiers, voltage controllers, and optoelectronics components.