130 results on '"Van den bosch, Geert"'
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2. Relaxation analysis to understand positive bias induced trapping in ferroelectric FETs with Si and Gd dopants
3. Random Telegraph Noise and Radiation Response of 80 nm Vertical Charge-Trapping NAND Flash Memory Devices With SiON Tunneling Oxide
4. A Theoretical Analysis of Ferroelectric Switching Physics in Metal/Ferroelectric/IGZO Stack Toward Interlayer-Free FeFETs
5. Modeling of in-plane distortions and overlay errors encountered during 3-D NAND flash device fabrication
6. Comprehensive understanding of charge lateral migration in 3D SONOS memories
7. Modeling the Operation of Charge Trap Flash Memory—Part II: Understanding the ISPP Curve With a Semianalytical Model
8. Engineering Strain and Texture in Ferroelectric Scandium-Doped Aluminium Nitride
9. High-k gadolinium and aluminum scandates for hybrid floating gate NAND flash
10. RTN assessment of traps in polysilicon cylindrical vertical FETs for NVM application
11. Electrolithic Memory: A New Device for Ultrahigh-Density Data Storage
12. Demonstration of 64 Conductance States and Large Dynamic Range in Si-doped HfO2 FeFETs under Neuromorphic Computing Operations
13. High-Endurance Ferroelectric (La, Y) and (La, Gd) Co-Doped Hafnium Zirconate Grown by Atomic Layer Deposition
14. Impacts of Pulsing Schemes on the Endurance of Ferroelectric Metal–Ferroelectric–Insulator–Semiconductor Capacitors
15. Understanding the Origin of Metal Gate Work Function Shift and Its Impact on Erase Performance in 3D NAND Flash Memories
16. Program/Erase Scheme for Suppressing Interface Trap Generation in HfO2-Based Ferroelectric Field Effect Transistor
17. Ferroelectric La-Doped ZrO2/HfxZr1-xO2 Bilayer Stacks with Enhanced Endurance
18. Multi-scale Modeling Approach to Assess and Mitigate Wafer Warpage in 3-D NAND Fabrication
19. Elucidating possible crystallographic origins of wake-up mechanisms in ferroelectric hafnia
20. Ferroelectric La‐Doped ZrO 2 /HfxZr1− xO 2 Bilayer Stacks with Enhanced Endurance
21. Hot-carrier degradation phenomena in lateral and vertical DMOS transistors
22. Impact of Mechanical Stress on 3-D NAND Flash Current Conduction
23. Highly Scaled Poly-Silicon Channel Vertical SONOS Cell for Ultra High Density NAND Technology
24. Program/Erase Scheme for Suppressing Interface Trap Generation in HfO2-Based Ferroelectric Field Effect Transistor.
25. On the hot-carrier-induced post-stress interface trap generation in n-channel MOS transistors
26. Direct and post-injection oxide and interface trap generation resulting from low-temperature hot-electron injection
27. Effect of Top Dielectric Morphology and Gate Material on the Performance of Nitride-based FLASH Memory Cells
28. Improvement of conduction in 3-D NAND memory devices by channel and junction optimization
29. Ferroelectric La‐Doped ZrO2/HfxZr1−xO2 Bilayer Stacks with Enhanced Endurance.
30. Precise measurement of thin-film thickness in 3D-NAND device with CD-SEM
31. First Demonstration of SiGe Channel in Macaroni Geometry for Future 3D NAND
32. Enabling CD SEM metrology for 5nm technology node and beyond
33. Oxide and interface degradation resulting from substrate hot-hole injection in metal-oxide-semiconductor field-effect transistors at 295 and 77 K.
34. Junctionless Array with Ultrathin Poly\TiN Floating Gate and HfAlO Based Intergate Dielectric for Sub-15nm Planar NAND Flash
35. In Depth Analysis of Post-Program VT Instability after Electrical Stress in 3D SONOS Memories
36. Material selection for hybrid floating gate NAND memory applications
37. Precise measurement of thin-film thickness in 3D-NAND device with CD-SEM.
38. Integration and Electrical Evaluation of Epitaxially Grown Si and SiGe Channels for Vertical NAND Memory Applications
39. Optimization of Ru Based Hybrid Floating Gate for Planar NAND Flash
40. Assessment methodology of the lateral migration component in data retention of 3D SONOS memories
41. Experimental study of programming saturation in low-coupling planar high-k/metal gate nand flash memory cells using a dedicated test structure
42. TID Radiation Response of 3-D Vertical GAA SONOS Memory Cells
43. ${\rm HfO}_{2}$ Based High-$k$ Inter-Gate Dielectrics for Planar NAND Flash Memory
44. Atomic layer deposition of scandium-based oxides
45. Read and Pass Disturbance in the Programmed States of Floating Gate Flash Memory Cells With High-$\kappa$ Interpoly Gate Dielectric Stacks
46. Reliability Comparison of ISSG Oxide and HTO as Tunnel Dielectric in 3-D–SONOS Applications
47. Innovative schemes to improve reliability and density of horizontal and vertical channel 3D Flash
48. Impact of Charge Trapping Layer Thickness and New Trade-Off in Performance Characteristics of 3-D SONOS Devices
49. Vertical polysilicon Pinch-Off FET for 3D memory technology: Feasibility and electrical performance
50. Ultimate Scaling Projection of Cylindrical 3D SONOS Devices
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