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Researchers have developed numerous effective theory-based practices for teaching undergraduate general education mathematics (UGEM); however, many universities have struggled for decades to close the gap from theory to practice. This gap contributes to the national lack of skilled STEM workers. Recently, an all-online university closed the gap by shifting their philosophical framework for UGEM from traditionalist methodology to a synthesis of seminal theories and practices. This paper disseminates the implementation of theory-based practices in UGEM toward reducing student attrition (withdraw or fail), including: Rationale for theory identification, construction of a philosophical framework, collection of stakeholder input, implementation, evaluation, post-implementation maintenance and communication, and institutional socialization of the new paradigmatic shift. These efforts yielded an attrition reduction from 17.5% to 4.7% in Quantitative Reasoning 1 (QR1) and from 13.9% to 4.0% in QR2. A key reported outcome is a blueprint for an institution to similarly close the gap.

Computer science textbooks with lengthy text explanations of concepts are often considered thorough and rigorous, so lengthy textbooks (and class notes) are commonplace. Some, however, suggest text should be concise because people tend to skim lengthy text. This article takes advantage of modern digital textbooks that measure reading time to examine reading rates for various text passage lengths. For a widely used CS textbook written in a nonconcise style, students read shorter passages (200 words or less) at about 200 words per minute, which is a typical rate. But for longer passages (600+ words), the rate increased to about 800 words per minute, suggesting skimming rather than reading. For another widely used CS textbook, from the same publisher but written in a concise style with text passage sizes kept below 250 words, students spent more time (around 200 words per minute) reading the text passages, and their time spent was well correlated with text length, suggesting students were carefully reading rather than skimming. Across three digital textbooks, the more interactive elements (e.g., integrated questions) that were included, the more time students spent reading the text between those activities. The conclusion is that to best educate students, authors of CS content should take the extra time needed to explain concepts more concisely--a case of "less is more"--and incorporate many active learning opportunities.

Physical models utilize mathematical equations to characterize physical systems like airwaymechanics, neuron networks, or chemical reactions. Previous work has shown that field programmable gate arrays (FPGAs) execute physical models efficiently. To improve the implementation of physical models on FPGAs, this article leverages graph theoretic techniques to synthesize physical models onto FPGAs. The first phase maps physical model equations onto a structured virtual processing element (PE) graph using graph theoretic folding techniques. The second phase maps the structured virtual PE graph onto physical PE regions on an FPGA using graph embedding theory. A simulated annealing algorithm is introduced that can map any physical model onto an FPGA regardless of the model's underlying topology.We further extend the simulated annealing approach by leveraging existing graph drawing algorithms to generate the initial placement. Compared to previous work on physical model implementation on FPGAs, embedding increases clock frequency by 25% on average (for applicable topologies), whereas simulated annealing increases frequency by 13% on average. The embedding approach typically produces a circuit whose frequency is limited by the FPGA clock instead of routing. Additionally, complex models that could not previously be routed due to complexity were made routable when using placement constraints.

With recent success in logic synthesis tools, many designers are focussing on capturing the design with a Register Transfer Level (RTL) description and using synthesis tools to complete the rest of the design. Due to the large amount of detail, writing a RTL description requires a long time, making it unacceptable when designs have to be produced rapidly. In this paper we propose a design methodology that can shorten the design cycle significantly. This is achieved by specifying the design at the highest level of abstractions and using powerful tools to complete the rest of the design. We have used this methodology on an industrial application, where we have designed and implemented a fuzzy logic controller.

Partitioning a system's functionality among interacting hardware and software components is an important part of system design. We introduce a new partitioning algorithm that caters to the main objective of the hardware/software partitioning problem, i.e. minimizing hardware for given performance constraints. We demonstrate results superior to those of previously published algorithms in tended for hardware/software partitioning.

VHDL and other hardware description languages ha ve become popular as system specification languages in top-down design. However, their constructs do not support the behavioral specification of embedded systems. We introduce a new conceptual design model, called Program-State Machines, that caters to embedded systems. We then describe the SpecCharts language, an extended version of VHDL, which supports capture of this design model. In conjunction with a translator to VHDL, SpecCharts can be easily incorporated into a VHDL design environment, with the advantages of significantly reduced specification time and fewer errors. The extensions introduced for VHDL are applicable to many other hardware description languages as well. We demonstrate the advantages of using SpecCharts for system specification capture through several experiments.

This report describes a presentation on the design methodology and the user's view of the SpecSyn system design framework. Given an abstract specification of a system, we present specification capture and the subsequent refinements that will result in the synthesizable descriptions. The advantages of the underlying methodology compared to current approaches are highlighted.

Given an abstract specification of a system, we present a methodology for specification capture and refinements that will result in synthesizable descriptions. It must be emphasized here that this report is about methodology - the set of descriptions and the manual refinements to derive one description from the other. Some of these refinements can be automated and collected as a set of system-level synthesis tools which are not a part of this report.

SpecCharts is a language intended for system level specification and synthesis. Its blending of hierarchical state-diagrams with programming constructs permits description of event-driven systems as a true hierarchy of behaviors, unlike existing languages. Through many examples, we show in this report how a language with an underlying model of behavioral hierarchy greatly aids concise and comprehensible specifications obtained with minimal effort.

VHDL signals and wait statements provide great expressive power for behavioral descriptions. However, due to their simulation semantics, most high-level synthesis tools do not handle these constructs and severely restrict their use, eliminating much of their power. In this report, we introduce a set of transformations to convert signals and wait statements to equivalent constructs that are easily handled by high-level synthesis tools. They greatly enlarge the synthesizable VHDL subset, thus increasing the usefulness and practicality of the language as an input to high-level synthesis. These transformations can also serve as a basis for converting a VHDL process to a form suitable for generation of software.

Signals are a fundamental part of VHDL behavioral descriptions. There are many kinds of VHDL signals, each possesing complex and hence often misunderstood semantics. The result is that synthesis tools often inadequately address synthesis of signals. In this report, we first make clear the semantics of the various signal kinds shared by multiple processes through the use of conceptual hardware, rather than just text. Second, with the semantics firmly understood, we discuss techniques and issues in synthesizing actual hardware for shared signals. This information can be used to take a step towards synthesizing correct hardware from VHDL descriptions while greatly reducing current restrictions imposed by synthesis tools on allowable VHDL behavior.

Given a system behavioral specification, partitioning can be used to distribute among chips the processes, procedures, and storage elements that comprise the specification. We introduce a technique for constant-time recomputation of pin, area, and execution-time estimates for a behavioral partitioning move. The technique permits fast, accurate estimations of a large number of partitionings, thus enabling better results than approaches which attain tractable computation time by using gross estimates or less thorough partitioning algorithms. The key to our technique is the isolation and extraction before partitioning of the basic design attributes needed for estimation, and the updating of this information in constant-time for each move. The estimation models are almost as detailed as those presented in previous estimation approaches not intended for constant-time update. The results we provide indicate the speed and practicality of our estimation approach in conjunction with sophisticated partitioning algorithms.

Many approaches have been developed to partition a system's behavioral description before a structural implementation is synthesized. We highlight the foundations and motivations for behavioral partitioning. We survey behavioral partitioning approaches, discussing abstraction levels, goals, major steps, and key assumptions in each.

The advent of VHDL has brought about a number of VHDL simulators. Many translation schemes from domain specific languages to supposedly functionally equivalent VHDL have been developed as an approach to obtaining simulations. However, functionally equivalent VHDL can not be created for the general case, due to a theoretical limitation to this approach. It is a very subtle point and has thus been overlooked until now, but it is extremely important since it can cause incorrect siniulation, therefore making translations to VHDL an unsound simulation technique. In this paper, we introduce this fundamental limitation. In addition, we propose an alternative approach which strives for functionally equivalent simulation rather than functionally equivalent VHDL, while still taking advantage of VHDL simulators. Our method uses a novel time-shift transformation, also introduced in this paper, in conjunction with almost any translation scheme. The method makes correct simulations easily obtainable, thus bridging the gap to a truly sound and highly advantageous use of VHDL as a tool for simulating domain specific languages.

SpecCharts is a new language intended for system level specification and synthesis. SpecCharts represent a multi-module system with a hierarchy of state diagrams, catering to the expression of concurrent behavior, and using VHDL sequential statement semantics to describe a leaf state's (a state not composed of substates) functionality. The language permits protocol based data transfer, estimations, constraints, and state based description, all of which enable the omission of detail and thus enhance the comprehension of a system's behavior. The language is intended to represent a design throughout the system and chip levels of synthesis. i.e. converting an abstract specification into a set of one or more interconnected chips/modules, each having a well defined structure or being bound to a prefabricated component. Since good system design requires an executable specification language, SpecCharts can be simulated via automatic conversion to VHDL.

SpecCharts is a language intended for system level description and synthesis. It is based on hierarchical state diagrams, posseses many constructs designed to facilitate ease of system level descriptions, and is simulatable via a translator from SpecCharts to VHDL. To test the feasability of using the language, several examples were modeled using SpecCharts, were converted to VHDL, and simulated to verify correctness. The details of two of those examples are provided in this report.

SpecCharts is a new language intended for system level specification and synthesis. It is based on hierarchical state diagrams and VHDL, and posseses many constructs designed to facilitate ease of description. Since current requirements demand that a specification language be simulatable, an approach for simulating SpecCharts needed to be developed. Rather than taking on the major task of writing a new simulator, a translator from SpecCharts to VHDL was implemented. This permits making use of the advantages that accompany the standardization of VHDL, including use of powerful compilers and simulators, while maintaining the ability to describe systems concisely and perform system level synthesis steps. The SpecChart to VHDL translator must convert each SpecChart abstraction to functionally equivalent VHDL. This report describes each of those abstractions and their VHDL implementation. The system takes as input a SpecChart and outputs a VHDL file which, when compiled, is a simulatable entity that can be used as any other VHDL entity. Several examples display how the translator can be used to verify SpecChart models of systems, thus adding to SpecCharts capability as a system level specification language.

The need has evolved for a synthesis tool at the computer system level. SpecSyn is one such tool. Basically, it will view the world as a set of chips communicating via protocols. Thus, an abstract specification would get synthesized into a set of one or more interconnected chips. From that point, detail is added to each chip's specification until its structure is synthesized or it is determined that a prefabricated chip similar in functionality can be used.Features of such a tool include executable specifications from which to synthesize, constraint driven partitioning of the specifications into components (chips) and synthesis of interfaces between them, translation into VHDL and synthesis into VHDL structures of micro-architectural components, and the use of other tools (e.g. MILO, a micro-architecture and logic optimizer, and LES, a layout expert system) to evaluate the quality of the chip layout generated from VHDL description.A major component of SpecSyn is SpecCharts, a high level specification language amenable to system level synthesis, able to represent designs from system to register transfer levels. The language consists of a hierarchy of states, represented in combined graphical and textual form, at the same time catering to the expression of concurrent behavior and specification of constraints. With it we have specified several Intel chips as well as higher level systems, and have found it to be quite powerful and easy to use.SpecSyn will have a graphical interface, from which the user can at any time view or edit a SpecChart, translate to VHDL and simulate, view statistics provided by estimators (such as area, speed, and pins), store and retrieve SpecCharts, apply basic Spec Chart operations, as well as apply the partitioning algorithms or interface synthesizer. Providing access to a wide range of tools, having a single language represent the design throughout the synthesis process, and having user specified constraints allow the user to have varying amounts of control over the synthesis process.